Compact and low loss y-junction for submicron silicon waveguide

Abstract

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

1 - 8 . (canceled) 
     
     
         9 . A method of designing a photonic device, the method comprising:
 identifying fabrication design rules of a fabrication process;   generating an initial device design constrained by the fabrication design rules; and   iteratively optimizing a device design starting with the initial device design.   
     
     
         10 . A method according to  claim 9  wherein iteratively optimizing the device design comprises:
 generating a smoothed geometry of the device design; and 
 simulating a functionality of the device utilizing the smoothed geometry of the device design. 
 
     
     
         11 . A method according to  claim 10  wherein iteratively optimizing the device design comprises utilizing particle swarm optimization on the device design. 
     
     
         12 . A method according to  claim 10  wherein generating the smoothed geometry of the device design comprises spline interpolation. 
     
     
         13 . A method according to  claim 10  wherein iteratively optimizing the device design is performed in accordance with the fabrication design rules. 
     
     
         14 . A method according to  claim 13  wherein the fabrication design rules comprise a minimum feature size. 
     
     
         15 . A method according to  claim 10  wherein generating an initial device design comprises determining a plurality of I/O ports and segments along a direction of optical signal propagation, the plurality of segments characterized by a corresponding respective plurality of widths. 
     
     
         16 . A method according to  claim 15  wherein iteratively optimizing the device design comprises utilizing an optimization algorithm on the plurality of widths. 
     
     
         17 . A method according to  claim 16  wherein the optimization algorithm comprises a particle swarm optimization algorithm. 
     
     
         18 . A method according to  claim 16  wherein the optimization algorithm comprises a genetic algorithm. 
     
     
         19 . A method according to  claim 16  wherein simulating a functionality of the device comprises determining at least one figure of merit (FOM), wherein iteratively optimizing the device design comprises evaluating optimization criteria with use of the at least one FOM, and for each iteration of said iteratively optimizing for which optimization criteria has not been met, modifying at least one of the plurality of widths according to the optimization algorithm. 
     
     
         20 . A method according to  claim 19  wherein simulating a functionality of the device comprises simulating the electromagnetic response of the device using a finite difference time domain (FDTD) method. 
     
     
         21 . A method according to  claim 20  wherein generating a smoothed geometry of the device design comprises spline interpolation. 
     
     
         22 . A method according to  claim 21  wherein the photonic device comprises a Y-junction and wherein the fabrication design rules comprise a minimum feature size of 200 nm. 
     
     
         23 . A method according to  claim 22  wherein the at least one FOM comprises power in TEO mode at either branch.