Field effect transistor with channel core modified for a backgate bias and method of fabrication

Abstract

A semiconductor device, includes a substrate, a source structure and a drain structure formed on the substrate. At least one interconnect structure interconnects the source structure and the drain structure and serves as a channel therebetween. A gate structure is formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel. Each of the interconnect structures include a center core serving as a backbias electrode for the channel.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a source structure and a drain structure formed on said substrate;   at least one interconnect structure interconnecting said source structure and said drain structure and serving as a channel therebetween; and   a gate structure formed over said at least one interconnect structure to provide a control of a conductivity of carriers in said channel,   wherein each of said at least one interconnect structure includes a center core serving as a backbias electrode for said channel.   
     
     
         2 . The semiconductor device of  claim 1 , wherein said center core comprises a polysilicon. 
     
     
         3 . The semiconductor device of  claim 1 , wherein said center core comprises a metal. 
     
     
         4 . The semiconductor device of  claim 3 , wherein said metal comprises tungsten (W). 
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 a film of insulation material having openings respectively over said source structure, said drain structure, said gate structure, and a contact with said center core; and    a conductive material respectively filling said openings and respectively contacting said source structure, said drain structure, said gate structure, and said center core, to serve as electrical connections to said semiconductor device.   
     
     
         6 . The semiconductor device of  claim 1 , wherein said channel structure comprises a nanowire, so that said semiconductor device comprises a nanowire field effect transistor (NWFET). 
     
     
         7 . The semiconductor device of  claim 1 , wherein said channel structure comprises a fin structure, so that said semiconductor device comprises a fin field effect transistor (finFET). 
     
     
         8 . The semiconductor device of  claim 1 , wherein said at least one interconnect structure comprises a plurality of interconnects between said source structure and said drain structure. 
     
     
         9 . The semiconductor device of  claim 1 , wherein said channel comprises one of Si, SiGe, and Si/SiGe. 
     
     
         10 . A method of fabricating a semiconductor device, said method comprising:
 forming a source structure and a drain structure on a substrate;   forming at least one interconnect structure interconnecting said source structure and said drain structure, said at least one interconnect structure serving as a channel therebetween; and   forming a gate structure over said at least one interconnect structure to provide a control  of a conductivity of carriers in said channel,   wherein each of said at least one interconnect structure includes a center core serving as a backbias electrode for said channel.   
     
     
         11 . The method of  claim 10 , wherein said forming said at least one interconnect structure comprises:
 forming a first structure between said source structure and said drain structure;   forming a second structure between said source structure and said drain structure, said second structure coating said first structure and having a composition different from a composition of said first structure, said different compositions having different etch rates;   etching out said first structure using an etch selective to said composition of said first structure; and   filling in a region etched out by said etching with an electrode material, to thereby serve as said backbias electrode of said center core.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming a dielectric layer to cover said source structure, said drain structure, said at least one interconnect structure, and said gate structure;   etching openings in said dielectric layer to expose access points to said source structure, said drain structure, said at least one interconnect structure, said gate structure, and said backbias electrode; and   depositing a conductive material to respectively fill said openings, thereby respectively  contacting said source structure, said drain structure, said gate structure, and said center core, and to serve as electrical connections to said semiconductor device.   
     
     
         13 . The method of  claim 10 , wherein said at least one interconnect structure interconnecting said source structure and said drain structure comprises a plurality of nano structures interconnecting between said source structure and said drain structure, each said nano structure comprising a channel structure with a center core.