4d device, process and structure

Abstract

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.

1 - 61 . (canceled) 
     
     
         62 . An article of manufacture comprising a 4D device. 
     
     
         63 . The device of  claim 62  which includes a vertically stacked 3D component comprising at least one of a 2D-in-4D format, 3D-in-4D format, and 2D/3D-in-4D format, connected to a horizontally stacked component comprising at least one of a 2D format and a 3D format. 
     
     
         64 . The device of  claim 63  wherein said horizontally stacked component comprises a 2D planar multicore logic device (2D). 
     
     
         65 . The device of  claim 63  wherein said horizontally stacked component comprises a 3D multi-stacked device with through-Si-vias (TSV) comprising at least one of TSV and 3D-TSV. 
     
     
         66 . The device of  claim 63  wherein said horizontally stacked component comprises at least one of a voltage regulating module (VRM), memory, logic, optoelectronics (O-E), III-V device, micro-electro-mechanical (MEMS) stacks with TSV in the 3D stacks which comprises a 3D-TSV-combination. 
     
     
         67 . The device of  claim 63  wherein said vertically stacked component comprises 2D device slices stacked without TSV between said 2D device slices in said vertical 4D stacking in said 2D-In-4D configuration. 
     
     
         68 . The device of  claim 63  wherein said vertically stacked component comprises 2D memory stacked without TSV between said 20 memory in said 4D vertical stacking and in said 2D-in-4D, memory configuration. 
     
     
         69 . The device of  claim 63  wherein said vertically stacked component comprises at least one of 2D devices comprising memory, voltage regulation module (VRM), opto-electronics (O-E), a III-V device, a micro-electrical-mechanical device (MEMS), in any combination without TSV between said 2D devices in said vertical 4D stacking and in said 2D-in-4D configuration. 
     
     
         70 . The device of  claim 63  wherein said vertically stacked component comprises 3D device slices with TSV within each of said 3D device slices and the said 3D devices form 4D stacking without TSV between said 4D devices in a 3D-in-4D format, wherein said primary 3D comprises traditional 3Di with TSV, 3DI-TSV, said secondary 3D comprises vertically stacked devices using surface wiring with edge I/O fan-out, and wherein said secondary 3Di can comprise a stand-alone device comprising memory stacks and said 4DI comprises a secondary 3DI with T&J connection to a horizontal logic, or other fine pitch connection. 
     
     
         71 . The device of  claim 70  wherein said vertically stacked component comprises primary 3D-TSV memory slices stacking with TSV within each of said 3D slices and said 3D-TSV memory slices form a 4D stacking without TSV or 4D between said 3D memories and comprises a 3D-in-4D-memory device, wherein said 4D used for said secondary 3D without TSV stacking comprises a different device than said 3D with said TSV. 
     
     
         72 . The device of  claim 70  wherein said vertically stacked component comprises any combination of primary 3D-TSV devices stacking comprising memory, VRM, O-E, III-V device, MEMS with TSV within the primary 3D device slices and said primary device slices form secondary 3D stacking without said TSV (4D) between said primary 3D stacking and comprises a 3D-in-4D combination device. 
     
     
         73 . The device of  claim 70  wherein said vertically stacked components comprises a combination of 2D and primary 3D-TSV device slices in a secondary 3D without TSV (4D) stacking and comprises 2D/3D combination-in-4D. 
     
     
         74 . The device of  claim 62  comprising any combination of a vertical component comprising 2D-in-4D, 3D-in-4D and 2D/3D-in-4D with a horizontal component comprising 2D and 3D, in any combinations of memory, logic, O-E, III-V device, VRM, and MEMS which comprises a combination of horizontal and vertical components of said device. 
     
     
         75 . The 4D device of  claim 62  which includes a 2D planar multi-core logic wafer and a vertically stacked 3D memory stack. 
     
     
         76 . The 4D device of  claim 75  wherein each of said memory wafers has a thickness sufficient so that all tier-1 regions are self-supporting, said thickness being more than about 150 um. 
     
     
         77 . The device of  claim 63  wherein fine pitch connections form connections between said vertically stacked 3D component and said horizontally stacked component where said vertically stacked component comprises a vertical memory stack and said horizontally stacked component comprise a horizontal logic. 
     
     
         78 . The device of  claim 77  wherein said fine pitch connections comprise micro-C4, Cu—Cu, Au—Au compression bonding, or conductive paste bonding 
     
     
         79 . The device of  claim 63  comprising a 4DI-TSV having an extremely high aspect ratio of from about 10:1 to about 100000:1 or from about 100:1 to about 100000:1 with a rectangular cross-section, and a rectangular width from about 1 um to about 100 um, height from about 0.5 um to about 20 um, and a length comprising the depth of a through-device-via from about 0.5 mm to about 20 mm. 
     
     
         80 . The device of  claim 62  wherein said 4D device comprises vertical stacked slices through fine pitch TJ edge connections operatively associated with a logic circuit, wherein said vertical slices comprise either 20 or 3D devices, and further comprising blank conductor sheets inserted between said vertical slices to provide a power/ground connection to the top of said logic circuit. 
     
     
         81 . The device of  claim 80  wherein said blank conductor sheets comprising a metal are from about 1 um to about 20 um thick, and are inserted between said vertical slices using an adhesive to provide said connection. 
     
     
         82 . The device of  claim 81  wherein said metal comprises Cu. 
     
     
         83 . The device of  claim 63  wherein fine pitch connections form connections between said vertically stacked 3D component and said horizontally stacked component where said vertically stacked component comprises a vertical memory stack and said horizontally stacked component comprise a horizontal logic, and one or more of said vertically stacked 3D component comprises a high speed data transfer structure between an external I/O and said logic. 
     
     
         84 . The device of  claim 83  wherein said high speed data transfer structure comprises an electrical device or an optical device.