Test circuit under pad

Abstract

Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention.

1 . (canceled) 
     
     
         2 . An integrated circuit device, comprising:
 a plurality of input/output (I/O) pads located on a semiconductor die;   a bond pad disposed over an end portion of each of the plurality of I/O pads; and   a plurality of package bond fingers each communicatively coupled to a respective bond pad of the plurality of I/O pads.   
     
     
         3 . The integrated circuit device according to  claim 2 , wherein the plurality of I/O pads are located along an outer edge of the semiconductor die. 
     
     
         4 . The integrated circuit device according to  claim 3 , wherein the plurality of I/O pads extend towards the outer edge of the semiconductor die. 
     
     
         5 . The integrated circuit device according to  claim 2 , further comprising:
 a core area provided on the semiconductor die.   
     
     
         6 . The integrated circuit device according to  claim 5 , wherein the core area is surrounded by the plurality of I/O pads. 
     
     
         7 . The integrated circuit device according to  claim 6 , wherein the bond pad that is provided on each of the plurality of I/O pads is closer to an outer edge of the semiconductor die than to the core area. 
     
     
         8 . The integrated circuit device according to  claim 2 , wherein the end portion of the plurality of I/O pads corresponds to an active circuit area. 
     
     
         9 . The integrated circuit device according to  claim 2 , wherein the plurality of package bond fingers are disposed outside of the semiconductor die. 
     
     
         10 . The integrated circuit device according to  claim 2 , further comprising:
 a plurality of external bond pads located along an outer edge of the semiconductor die.   
     
     
         11 . The integrated circuit device according to  claim 10 , wherein the plurality of external bond pads are communicatively coupled to the bond pad. 
     
     
         12 . The integrated circuit device according to  claim 11 , further comprising:
 a core area provided on the semiconductor die.   
     
     
         13 . The integrated circuit device according to  claim 12 , wherein the plurality of I/O pads are located between the plurality of external bond pads and the core area. 
     
     
         14 . The integrated circuit device according to  claim 13 , wherein the core area is surrounded by the plurality of I/O pads. 
     
     
         15 . The integrated circuit device according to  claim 2 , further comprising:
 a plurality of external bond pads located at an inactive area of the semiconductor die.   
     
     
         16 . The integrated circuit device according to  claim 15 , wherein the plurality of external bond pads are located along an outer edge of the semiconductor die. 
     
     
         17 . The integrated circuit device according to  claim 15 , wherein the inactive area of the semiconductor die is free of active circuit components, the active circuit components being at least one of a transistor, a diode, a resistor, a capacitor, an inductor, and a conductive path. 
     
     
         18 . The integrated circuit device according to  claim 17 , further comprising:
 a core area provided on the semiconductor die.   
     
     
         19 . The integrated circuit device according to  claim 18 , wherein the core area is surrounded by the plurality of external bond pads. 
     
     
         20 . An integrated circuit device, comprising:
 an input/output (I/O) pad located on a semiconductor die;   a bond pad disposed over an end portion of the I/O pad; and   a package bond finger communicatively coupled to the bond pad.   
     
     
         21 . An integrated circuit device, comprising:
 a plurality of input/output (I/O) pads located on a semiconductor die;   an internal wire bond pad disposed over an end portion of each of the plurality of I/O pads;   a plurality of external wire bond pads located along an outer edge of the semiconductor die; and   a plurality of package bond fingers communicatively coupled to the plurality of external wire bond pads.