Semiconductor device and manufacturing method for the same

Abstract

A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

1 - 17 . (canceled) 
     
     
         18 . A semiconductor device comprising:
 a substrate including a first circuit region, and a first circuit element formed in the first circuit region;   a second circuit region, and a second circuit element formed in the second circuit region;   a multilayer wiring layer formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated; and   an electrode pad formed on the multilayer wiring layer,   wherein an interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad,   wherein the electrode pad overlaps the first circuit region and the second circuit region in the planar view of the electrode pad, and   wherein the first circuit region is formed in an internal circuit region, and the second circuit region is formed in an I/O circuit region.   
     
     
         19 . The semiconductor device according to  claim 18 , wherein the electrode pad overlaps the first circuit region and the second circuit region in the planar view of the electrode pad. 
     
     
         20 . The semiconductor device according to  claim 18 ,
 wherein the electrode pad includes a first pad region and a second pad region in which a larger stress is imposed than a stress imposed on the first pad region, and   wherein an interlayer insulating film is formed in a region of the first wiring layer, in the region in which the second pad region and the first circuit region overlap with each other in the planar view of the electrode pad.   
     
     
         21 . The semiconductor device according to  claim 19 ,
 wherein a first conductor pattern is formed in at least a part of a region of the first wiring layer, in a region other than the second pad region and the first circuit region which overlap with each other in the planar view of the electrode pad.   
     
     
         22 . The semiconductor device according to  claim 21 ,
 wherein a second conductor pattern is formed across the first and second pad regions in a second wiring layer, which is a wiring layer immediately below the first wiring layer, and   wherein the first and second conductor patterns are connected through a via.   
     
     
         23 . The semiconductor device according to  claim 18 , wherein the first pad region is formed on a side of the first circuit region and the second pad region is formed on a side of the second circuit region in the planar view of the electrode pad. 
     
     
         24 . The semiconductor device according to  claim 18 , wherein a projection is formed to a part corresponding to the second pad region in a periphery of the electrode pad. 
     
     
         25 . The semiconductor device according to  claim 18 ,
 wherein a length of the first pad region in a direction vertical to a longitudinal direction of the electrode pad is different from a length of the second pad region in the direction vertical to the longitudinal direction of the electrode pad.   
     
     
         26 . The semiconductor device according to  claim 25 , wherein the I/O circuit region is disposed along a circumference of the semiconductor device to surround the internal circuit region. 
     
     
         27 . The semiconductor device according to  claim 25 ,
 wherein the first circuit element formed in the internal circuit region includes at least one of a memory circuit and a logic circuit, and   wherein the second circuit element formed in the I/O circuit region includes at least one of an input buffer circuit, an output buffer circuit, and a level shifter.   
     
     
         28 . The semiconductor device according to  claim 18 , wherein an analog circuit is formed in a region where the first pad region of the substrate is formed in the planar view of the electrode pad. 
     
     
         29 . The semiconductor device according to  claim 28 , wherein the analog circuit includes at least one of a PLL circuit and a regulator circuit. 
     
     
         30 . The semiconductor device according to  claim 18 , wherein the first circuit element formed in the first circuit region is a power switch circuit.