Multilayer capacitor, method for manufacturing the same, and electronic device using the same

Abstract

Disclosed herein are a multilayer capacitor, a method for manufacturing the same, and an electronic device using the same. A multilayer capacitor including internal electrodes stacked in a dielectric so as to be spaced apart from each other, alternately connected to external electrodes formed on both sides of the dielectric, and formed so that width sizes of connection sections connected to the external electrodes are decreased as compared with those of overlapped sections overlapped with each other while vertically neighboring to each other in at least portions of a stacked structure is suggested. In addition, an electronic device using the multilayer capacitor and a method for manufacturing the multilayer capacitor are suggested.

What is claimed is: 
     
         1 . A multilayer capacitor comprising:
 a dielectric;   external electrodes formed on both sides of the dielectric; and   internal electrodes stacked in the dielectric, alternately connected to the external electrodes formed on both sides of the dielectric, and formed so that width sizes of connection sections connected to the external electrodes are decreased as compared with those of overlapped sections facing up and down.   
     
     
         2 . The multilayer capacitor according to  claim 1 , wherein the internal electrodes are formed so that the width sizes of the connection sections are decreased as compared with those of the overlapped sections in at least upper and lower regions of the stacked structure. 
     
     
         3 . The multilayer capacitor according to  claim 2 , wherein the internal electrodes are formed so that the width sizes of the connection sections are decreased as compared with those of the overlapped sections in an entire region of the stacked structure. 
     
     
         4 . The multilayer capacitor according to any one of  claims 1 , wherein pattern removing regions formed by decreasing the width sizes of the connection sections are formed on at least two layers of the stacked structure and are formed so as not to be vertically continuously overlapped with each other in the stacked structure. 
     
     
         5 . The multilayer capacitor according to  claim 4 , wherein the pattern removing regions are alternately formed at both sides of the connection sections in a width direction. 
     
     
         6 . The multilayer capacitor according to any one of  claims 1 , wherein the width sizes of the connection sections are decreased as compared with those of the overlapped sections by ¼ or more to ⅔ or less. 
     
     
         7 . The multilayer capacitor according to  claim 6 , wherein the width sizes of the connection sections are decreased as compared with those of the overlapped sections by ½. 
     
     
         8 . An electronic device using the multilayer capacitor according to any one of  claims 1 . 
     
     
         9 . An electronic device using the multilayer capacitor according to any one of  claims 2 . 
     
     
         10 . An electronic device using the multilayer capacitor according to any one of  claims 3 . 
     
     
         11 . A method for manufacturing a multilayer capacitor, comprising:
 forming internal electrode patterns on a plurality of dielectric sheets so that width sizes of connection sections that are to be connected to external electrodes are smaller than those of overlapped sections that are to be facing up and down;   forming the stacked dielectric by stacking the plurality of dielectric sheets having the internal electrode patterns formed thereon so that the connection sections are alternately disposed at both sides; and   forming the external electrodes on both sides of the stacked dielectric so as to be alternately electrically connected to the connection sections of the internal electrode patterns at both sides.   
     
     
         12 . The method for manufacturing a multilayer capacitor according to  claim 11 , wherein in the forming of the stacked dielectric, the plurality of dielectric sheets are stacked so that the width sizes of the connection sections are smaller than those of the overlapped sections in at least upper and lower layers of the stacked dielectric. 
     
     
         13 . The method for manufacturing a multilayer capacitor according to  claim 12 , wherein in the forming of the stacked dielectric, the plurality of dielectric sheets are stacked so that the width sizes of the connection sections are smaller than those of the overlapped sections in an entire stacked structure of the stacked dielectric. 
     
     
         14 . The method for manufacturing a multilayer capacitor according to any one of  claims 11 , wherein in the forming of the stacked dielectric, the plurality of dielectric sheets are stacked so that pattern removing regions in which the dielectric sheets are exposed due to a decrease in the width sizes of the connection sections in the forming of the internal electrode patterns are not continuously overlapped with each other in a vertical direction, but have connection section regions of the internal electrode patterns interposed therebetween. 
     
     
         15 . The method for manufacturing a multilayer capacitor according to any one of  claims 11 , wherein in the forming of the internal electrode patterns, the internal electrode patterns are formed so that the width sizes of the connection sections are in a range of approximately ⅓ to ¾ of those of the overlapped sections.