Semiconductor device including negative bias voltage generation circuit

Abstract

A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a memory macro including a memory cell array in which a predetermined array number of basic memory cell arrays each having memory cells arranged in a first number of rows are arranged in a column direction,   the memory macro including:
 a first bit line and a second bit line connected to the memory cells of the memory cell array; 
 a write driver configured to output writing voltages to the first and second bit lines; 
 a bias voltage generation circuit configured to generate a bias voltage; and 
 a bias reference voltage generation unit configured to generate a bias reference voltage, and output the bias reference voltage to the write driver, 
   wherein the bias reference voltage generation unit generates the bias reference voltage based on a resistance ratio between a first resistor and a second resistor each formed of the predetermined array number of unit resistors, and   wherein the write driver is configured to output the writing voltages according to the bias reference voltage.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein at least one of the basic memory cells is supplied with a first power supply voltage and a second power supply voltage which is greater than the first power supply voltage, and
 wherein one of the writing voltages is lower than the first voltage during writing.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the unit resistors are connected in parallel. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the unit resistors are arranged adjacent to the basic memory cell arrays in the column direction. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein an arrangement pitch of the unit resistors is identical to an arrangement pitch of the basic memory cell arrays. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein
 the unit resistors each include transistors, and   the transistors included in the first resistor have gate electrodes, respectively, that extend in a row direction and are arranged in the column direction at regular intervals.