Resistive switching by breaking and re-forming covalent bonds

Abstract

A variable resistance layer in a resistive non-volatile memory (ReRAM) cell changes its resistance in response to an applied signal by breaking and re-forming covalent bonds (e.g., in sub-stoichiometric silicon oxide). Resistivity decreases with increasing density of broken “dangling” bonds. When an electric field is applied, more dangling bonds are created, forming a filament of defects through which charge carriers can tunnel through the covalent layer. Passing a high current through the dangling-bond filament causes localized heating that re-forms the bonds. Optionally, an ionic oxide or nitride layer in contact with the covalent switching layer may serve as an oxygen source for thermal re-oxidation during the heating.

What is claimed is: 
     
         1 . A device, comprising:
 a substrate;   a first layer formed over the substrate, the first layer operable as a first electrode;   a second layer formed over the first layer, the second layer operable as a second electrode; and   a third layer formed between the first layer and the second layer;   wherein the third layer reversibly changes resistance responsive to a first write signal or a second write signal;   wherein a first write signal breaks covalent bonds in the third layer; and   wherein a second write signal re-forms broken covalent bonds in the third layer.   
     
     
         2 . The device of  claim 1 , wherein the third layer comprises silicon and at least one of oxygen or nitrogen. 
     
     
         3 . The device of  claim 1 , wherein a portion of the third layer near an interface is heated to between 500C and 900C by the second write signal, as calculated from thermal conductivities of the interface materials, a reset pulse current, a reset pulse length, and a cross-sectional area of a conductive filament at the interface. 
     
     
         4 . The device of  claim 1 , further comprising a fourth layer formed between the first layer and the second layer;
 wherein a dielectric constant of the fourth layer is greater than or equal to 9.   
     
     
         5 . The device of  claim 4 , wherein the fourth layer has a stoichiometric composition. 
     
     
         6 . The device of  claim 4 , wherein the third layer comprises a silicon oxide or a silicon oxynitride; and wherein the fourth layer comprises a transition metal oxide or a transition metal oxynitride. 
     
     
         7 . The device of  claim 4 , wherein the third layer comprises a silicon nitride; and wherein the fourth layer comprises a transition metal nitride. 
     
     
         8 . The device of  claim 4 , wherein a portion of the third layer near an interface with the fourth layer is heated to between 500C and 900C by the second write signal, as calculated from thermal conductivities of the interface materials, a reset pulse current, a reset pulse length, and a cross-sectional area of a conductive filament at the interface. 
     
     
         9 . The device of  claim 1 , wherein the covalent bonds comprise silicon-silicon bonds. 
     
     
         10 . A method, comprising:
 forming a first layer over a substrate;   forming a second layer over the first layer;   forming a third layer over the second layer; and   forming a fourth layer over the third layer;   wherein the first layer is operable as a first electrode;   wherein the second layer comprises a sub-stoichiometric covalent-bonded silicon oxide, silicon nitride or silicon oxynitride;   wherein the third layer has a dielectric constant greater than 9;   wherein the fourth layer is operable as a second electrode; and   wherein a thickness of the second layer is between about 5 nm and about 10 nm.   
     
     
         11 . The method of  claim 10 , wherein the forming of the second layer comprises physical vapor deposition at a substrate temperature between 400C and 520C. 
     
     
         12 . The method of  claim 11 , wherein the forming of the second layer comprises reactive sputtering from a silicon target in an oxygen-containing ambient. 
     
     
         13 . The method of  claim 11 , wherein the forming of the second layer comprises co-sputtering from a silicon target and a silicon-oxide target in an inert-gas ambient. 
     
     
         14 . The method of  claim 10 , wherein the forming of the second layer comprises plasma-enhanced chemical vapor deposition at a substrate temperature between 200C and 270C. 
     
     
         15 . The method of  claim 14 , wherein a gas mixture used for the plasma-enhanced chemical vapor deposition comprises silane and nitrous oxide. 
     
     
         16 . The method of  claim 14 , wherein a plasma used for the plasma-enhanced chemical vapor deposition comprises a 30-35 MHz radio-frequency plasma. 
     
     
         17 . The method of  claim 10 , wherein the forming of the second layer comprises electron-beam evaporation at a substrate temperature between 100C and 150C. 
     
     
         18 . The method of  claim 10 , wherein the forming of the second layer comprises rapid thermal annealing of amorphous silicon in an oxygen-containing ambient. 
     
     
         19 . The method of  claim 18 , wherein a substrate temperature during the rapid thermal annealing is between 520C and 620C. 
     
     
         20 . The method of  claim 18 , wherein a duration of the rapid thermal annealing is between 30 seconds and 30 minutes.