Cmos transistor and method for fabricating the same, display panel and display device

Abstract

The present invention provides a CMOS transistor and a method for fabricating the same, a display panel and a display device. The CMOS transistor comprises a first region and a second region provided on a base substrate, the first region comprises a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprises a second gate electrode, a second active layer, a second source electrode and a second drain electrode, first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer. The technical solution of the present invention can reduce power consumption of display panel.

1 - 18 . (canceled) 
     
     
         19 . A CMOS transistor, comprising a first region and a second region provided on a base substrate, the first region comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode,
 wherein first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, and a concentration of the first dopant ions is smaller than that of the second dopant ions; the first active layer is an n-type active layer, and the second active layer is a p-type active layer.   
     
     
         20 . The CMOS transistor of  claim 19 , wherein an etch stop layer is formed between the first active layer and the first source and drain electrodes and between the second active layer and the second source and drain electrodes. 
     
     
         21 . The CMOS transistor of  claim 19 , wherein the first active layer and the second active layer are oxide material layer. 
     
     
         22 . The CMOS transistor of  claim 21 , wherein the oxide material layer is zinc oxide layer. 
     
     
         23 . The CMOS transistor of  claim 20 , wherein a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively. 
     
     
         24 . The CMOS transistor of  claim 19 , wherein the first dopant ions and the second dopant ions are both N ions. 
     
     
         25 . A display device, comprising a display panel, the display panel comprising CMOS transistors, the CMOS transistor comprising a first region and a second region provided on a base substrate, the first region comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode,
 wherein first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, and a concentration of the first dopant ions is smaller than that of the second dopant ions; the first active layer is an n-type active layer, and the second active layer is a p-type active layer.   
     
     
         26 . The display device of  claim 25 , wherein an etch stop layer is formed between the first active layer and the first source and drain electrodes and between the second active layer and the second source and drain electrodes. 
     
     
         27 . The display device of  claim 25 , wherein the first active layer and the second active layer are oxide material layer. 
     
     
         28 . The display device of  claim 25 , wherein the first dopant ions and the second dopant ions are both N ions. 
     
     
         29 . A method for fabricating a CMOS transistor, comprising steps of:
 forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and   injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.   
     
     
         30 . The method for fabricating the CMOS transistor of  claim 29 , wherein the step of forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate comprises:
 forming the first gate electrode and the second gate electrode on the base substrate by a patterning process;   forming the first active layer and the second active layer on the base substrate on which the first gate electrode and the second gate electrode are formed; and   forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode on the first active layer and the second active layer by a patterning process.   
     
     
         31 . The method for fabricating the CMOS transistor of  claim 29 , wherein a planarization layer is formed on the first source electrode, the second source electrode, the first drain electrode and the second drain electrode before injecting the dopant ions;
 the step of injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process comprises:   forming a photoresist layer on the planarization layer, the photoresist layer comprising a first photoresist region and a second photoresist region, the first photoresist region corresponding to the first active layer, and the second photoresist region corresponding to the second active layer;   performing the doping process on the first active layer through the first photoresist region to inject N ions into the first active layer;   performing the doping process on the second active layer through the second photoresist region to inject N ions into the second active layer; and   removing the photoresist layer.   
     
     
         32 . The method for fabricating the CMOS transistor of  claim 31 , wherein the step of forming the photoresist layer on the planarization layer comprises:
 applying photoresist on the planarization layer; and   performing mask plate masking and exposure by using a half tone mask and performing development to form the first photoresist region and the second photoresist region.   
     
     
         33 . The method for fabricating the CMOS transistor of  claim 32 , wherein a thickness of the first photoresist region is larger than that of the second photoresist region. 
     
     
         34 . The method for fabricating the CMOS transistor of  claim 33 , wherein the thickness of the photoresist layer is equal to or larger than 3 μm, the thickness of the first photoresist region is ranged from 1.7 μm to 2.3 μm, and the thickness of the second photoresist region is ranged from 0.7 μm to 1.3 μm. 
     
     
         35 . The method for fabricating the CMOS transistor of  claim 29 , wherein the first active layer and the second active layer are made of oxide material. 
     
     
         36 . The method for fabricating the CMOS transistor of  claim 35 , wherein the oxide material is zinc oxide. 
     
     
         37 . The method for fabricating the CMOS transistor of  claim 29 , wherein before forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode, an etch stop layer is formed on the first active layer and the second active layer by a patterning process, and a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively. 
     
     
         38 . The method for fabricating the CMOS transistor of  claim 29 , wherein the first dopant ions and the second dopant ions are both N ions.