Photoelectric conversion device

Abstract

A photoelectric conversion device includes an element surrounding an active region including first and second areas verging each other at a virtual line, a charge accumulation region arranged in the first area, a floating diffusion region arranged across the first and second areas, a transfer gate electrode, and a first semiconductor region including a portion arranged between the charge accumulation region and the element isolation so as to surround at least part of the charge accumulation region, and a portion arranged in the second area. A width of the second area in a direction parallel to the virtual line is smaller than a width of the first area in the direction.

What is claimed is: 
     
         1 . A photoelectric conversion device comprising:
 an element isolation arranged to surround an active region including a first area and a second area which verge each other at a virtual line;   a charge accumulation region of a first conductivity type arranged in the first area;   a floating diffusion region of the first conductivity type arranged across the first area and the second area;   a gate electrode configured to form a channel for transferring charges accumulated in the charge accumulation region to the floating diffusion region; and   a first semiconductor region including a portion arranged between the charge accumulation region and the element isolation, so as to surround at least part of the charge accumulation region, and including a portion arranged in the second area, the first semiconductor region having a second conductivity type different from the first conductivity type,   wherein a width of the second area in a direction parallel to the virtual line is smaller than a width of the first area in the direction,   a boundary line defining an outer edge of the second area includes a first boundary line having a first point on the virtual line as one end and a second point which is not on the virtual line as the other end and a second boundary line having a third point on the virtual line as one end and a fourth point which is not on the virtual line as the other end,   the gate electrode includes a first portion spanning the first area and the second area so as to cover the first point, a second portion spanning the first area and the second area so as to cover the third point, and a third portion arranged above the first area so as to connect the first portion to the second portion, and   a boundary line defining an outer edge of the first semiconductor region includes a portion passing between the third portion and the virtual line.   
     
     
         2 . The device according to  claim 1 , wherein the charge accumulation region, the floating diffusion region, and the first semiconductor region are arranged in a second semiconductor region of the second conductivity type,
 an impurity concentration of the second conductivity type in the first semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor region, and   the channel is formed under the gate electrode in the second semiconductor region.   
     
     
         3 . The device according to  claim 2 , wherein the second semiconductor region does not contact the element isolation. 
     
     
         4 . The device according to  claim 1 , further comprising a third semiconductor region of the second conductivity type arranged on the charge accumulation region. 
     
     
         5 . The device according to  claim 4 , wherein the third semiconductor region is arranged so as to contact the first semiconductor region in the first area. 
     
     
         6 . The device according to  claim 1 , wherein the charge accumulation region is separated from the first semiconductor region in a direction parallel to the virtual line. 
     
     
         7 . The device according to  claim 6 , wherein a width of the charge accumulation region in a direction parallel to the virtual line is smaller than a width of the gate electrode, within an area of the first area, in the direction parallel to the virtual line. 
     
     
         8 . The device according to  claim 5 , wherein the charge accumulation region includes a first accumulation region and a second accumulation region arranged between the first accumulation region and the gate electrode, and
 a width of the first accumulation region in a direction parallel to the virtual line is smaller than a width of the second accumulation region in the direction parallel to the virtual line.   
     
     
         9 . The device according to  claim 1 , wherein the floating diffusion region includes a first diffusion region, and a second diffusion region arranged between the first diffusion region and the gate electrode, and
 a width of the second diffusion region in a direction parallel to the virtual line is larger than a width of the first diffusion region in the direction parallel to the virtual line.   
     
     
         10 . The device according to  claim 1 , wherein the first portion and the second portion extend in a direction perpendicular to the virtual line, and the third portion extends in a direction parallel to the virtual line. 
     
     
         11 . The device according to  claim 10 , wherein the third portion has a portion whose width in a direction parallel to the virtual line decreases with an increase in distance from the floating diffusion region. 
     
     
         12 . The device according to  claim 1 , wherein the gate electrode has an arcuated shape. 
     
     
         13 . The device according to  claim 1 , wherein a portion arranged between the charge accumulation region and the element isolation so as to surround at least part of the charge accumulation region of the first semiconductor region includes a pair of opposing portions facing each other so as to sandwich the charge accumulation region, and the first semiconductor region includes a portion with an interval between the pair of opposing portions decreasing toward the floating diffusion region. 
     
     
         14 . The device according to  claim 13 , wherein the first area has a portion whose width in a direction parallel to the virtual line gradually decreases toward the floating diffusion region. 
     
     
         15 . The device according to  claim 1 , wherein the semiconductor region and the charge accumulation region have portions extending in a direction obliquely intersecting the virtual line. 
     
     
         16 . The device according to  claim 1 , wherein the floating diffusion region does not contact the element isolation. 
     
     
         17 . The device according to  claim 1 , further comprising a transistor configured to connect a capacitor to the floating diffusion region, the transistor being arranged in the active region. 
     
     
         18 . The device according to  claim 1 , further comprising a first transistor configured to connect a capacitor to the floating diffusion region and a second transistor configured to reset a potential of the floating diffusion region,
 the first transistor and the second transistor being arranged in the active region.   
     
     
         19 . The device according to  claim 1 , further comprising a first transistor configured to connect a capacitor to the floating diffusion region and a second transistor configured to reset a potential of the floating diffusion region,
 at least one of the first transistor and the second transistor being arranged in an active region separated from the active region.   
     
     
         20 . The device according to  claim 1 , wherein the virtual line comprises a straight line.