Semiconductor device and method of manufacturing the same

Abstract

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) th second sidewall film matching a pattern of a n th (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2 n )×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

1 .- 20 . (canceled) 
     
     
         21 . A method of manufacturing a semiconductor device comprising:
 forming a first sidewall film including a first line width by a first sidewall formation process, on a lateral surface of a first layer in a first area and a second area of a semiconductor substrate;   forming a first mask including a second line width greater than the first line width on the first sidewall film in the second area by lithography after the first layer is removed;   forming a first pattern by processing a first pattern layer using the first sidewall film and the first mask;   forming a plurality of second sidewall films including a third line width which is the first line width or less, by a second sidewall formation process on a lateral surface of the first pattern; and   processing a processing target layer above the semiconductor substrate using the second sidewall film as a mask, and forming a plurality of interconnects which comprise:
 at least one of a first interconnect width or a first interconnect interval in the first area, the first interconnect interval having a first dimension, and 
 a second interconnect interval in the second area, the second interconnect interval having a second dimension greater than the first dimension.