Semiconductor device

Abstract

In a nonvolatile memory device provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

1 . A semiconductor device comprising:
 a memory cell transistor having a charge storage portion and storing data based on a change of a threshold voltage depending on an amount of charge in said charge storage portion;   a voltage generation unit generating a boosted voltage to be supplied to one main electrode of said memory cell transistor in an erase operation based on a band-to-band tunneling scheme;   a detection unit detecting an output voltage of said voltage generation unit and comparing the output voltage with a reference value; and   a control unit controlling a timing at which said boosted voltage is supplied in said erase operation,   said control unit ending supply of said boosted voltage when a predetermined first reference time has elapsed since start of supply of said boosted voltage and a result of detection and comparison by said detection unit indicates that said boosted voltage has become equal to or more than said reference value.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein said voltage generation unit includes a charge pump circuit. 
     
     
         3 . A semiconductor device comprising:
 a plurality of memory cell transistors each having a charge storage portion and storing data based on a change of a threshold voltage depending on an amount of charge in said charge storage portion,
 said plurality of memory cell transistors being divided into n groups, transistors belonging to the same group each having one main electrode connected to a common line; 
   a voltage generation unit generating a boosted voltage to be supplied to said common line of each said group in an erase operation based on a band-to-band tunneling scheme;   a detection unit detecting an output voltage of said voltage generation unit and comparing the output voltage with a reference value; and   a control unit controlling a timing at which said boosted voltage is supplied in said erase operation,   said control unit starting supply of said boosted voltage to an (i+1)-th group (1≦i≦n−1) when a predetermined first reference time has elapsed since start of supply of said boosted voltage to an i-th group and a result of detection and comparison by said detection unit indicates that said boosted voltage has become equal to or more than said reference value.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein said control unit ends supply of said boosted voltage to the i-th group (1≦i≦n−1) when supply of said boosted voltage to the (i+1)-th group is started. 
     
     
         5 . The semiconductor device according to  claim 3 , wherein said control unit ends supply of said boosted voltage to a j-th group (1≦j≦n) when a predetermined second reference time longer than said first reference time has elapsed since start of supply of said boosted voltage to the j-th group. 
     
     
         6 . The semiconductor device according to  claim 3 , further comprising n drivers corresponding respectively to said n groups and each supplying said boosted voltage to a corresponding group when a control signal supplied to each driver is an active state, wherein
 said control unit includes n control signal generation units corresponding respectively to said n drivers and each generating said control signal to be output to a corresponding driver, and   said n control signal generation units each include a flip-flop, said control signal which is output to a corresponding driver is activated when said flip-flop is a first state and said control signal which is output to a corresponding driver is deactivated when said flip-flop is a second state.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein
 said n control signal generation units each include:
 a first input node to which a common first control pulse is input; 
 a second input node to which a common second control pulse is input; 
 a third input node; and 
 an output node from which said control signal is output, 
   a start signal is input to said third input node of a first control signal generation unit,   said control signal which is output from a k-th (1≦k≦n−1) control signal generation unit is input to said third input node of a (k+1)-th control signal generation unit,   said n control signal generation units each switch said flip-flop from said second state to said first state upon receiving said first control pulse when said flip-flop is said second state and the signal which is input to said third input node is an active state, and   said n control signal generation units each switch said flip-flop from said first state to said second state upon receiving said second control pulse when said flip-flop is said first state and the signal which is input to said third input node is an inactive state.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein
 said control unit further includes a control pulse generation unit generating said first and second control pulses,   said control pulse generation unit outputs said second control pulse together with said first control pulse in a first erase mode, and   said control pulse generation unit outputs said second control pulse when a predetermined second reference time longer than said first reference time has elapsed since output of said first control pulse in a second erase mode.   
     
     
         9 . The semiconductor device according to  claim 3 , wherein said voltage generation unit includes a charge pump circuit. 
     
     
         10 . A semiconductor device comprising:
 a plurality of memory cell transistors each having a charge storage portion and storing data based on a change of a threshold voltage depending on an amount of charge in said charge storage portion,
 said plurality of memory cell transistors being divided into n groups, transistors belonging to the same group each having one main electrode connected to a common line; 
   a voltage generation unit generating a boosted voltage to be supplied to said common line of each said group in an erase operation based on a band-to-band tunneling scheme;   a detection unit detecting an output current of said voltage generation unit and comparing the output current with a reference value; and   a control unit controlling a timing at which said boosted voltage is supplied in said erase operation,   said control unit starting supply of said boosted voltage to an (i+1)-th group (1≦i≦n−1) when a predetermined first reference time has elapsed since start of supply of said boosted voltage to an i-th group and a result of detection and comparison by said detection unit indicates that said output current has become equal to or less than said reference value.