Semiconductor integrated circuit

Abstract

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

What is claimed is: 
     
         1 . A semiconductor devise comprising:
 a data transmitting circuit that transmits transmission data in parallel through a plurality of signal lines; and   wherein the data transmitting circuit comprises:   a plurality of data output circuits that output the transmission data in a data transmission mode or set an output to a high impedance state in a high impedance mode, the data output circuits being provided to the corresponding signal lines;   a plurality of data selection circuits that select one of the transmission data and fixed data preliminarily set and output the selected data to the corresponding data output circuits; and   a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the high impedance mode to the data transmission mode and a time when the data output circuits start to output the transmission data,   wherein the semiconductor circuit is a memory devise.   
     
     
         2 . The semiconductor devise according to  claim 1 , wherein
 each of the data selections circuits comprises:
 a register that outputs the fixed data; and 
 a selector that selects one of the fixed data stored in the register and the transmission data based on a control signal output from the control circuit and outputs the selected data. 
   
     
     
         3 . The semiconductor devise according to  claim 1 , wherein
 the control circuit changes a mode of each of the data output circuits to one of the high impedance mode and the data transmission mode.   
     
     
         4 . The semiconductor devise according to  claim 1 , wherein
 when the data transmitting circuit transmits the transmission data, the control circuit changes a mode of each of the data outputs circuits to the data transmission mode, whereas when the data transmission circuit does not transmit the transmission data, the control circuit changes the mode of each of the data outputs circuits to the high impedance mode.   
     
     
         5 . The semiconductor devise according to  claim 1 , wherein
 the data transmission circuit further comprises a plurality of external terminals each disposed on a corresponding one of the plurality of signal lines, and   the control circuit controls so as to output the fixed data to each of the plurality of external terminals in such a manner that each of the plurality of external terminals is supplied with fixed data having a different potential from that for an adjacent external terminal.   
     
     
         6 . The semiconductor devise according to  claim 1 , wherein
 each of the transmission circuits further comprises an inverter comprising a P-channel MOS transistor and an N-channel MOS transistor, and   in the high impedance mode, both the P-channel MOS transistor and the N-channel MOS transistor are turned off; and in the data transmission mode, one of the P-channel MOS transistor and the N-channel MOS transistor is turned on and the other of the channel MOS transistor and the N-channel MOS transistor is tuned off based on one of the transmission data and the fixed data.   
     
     
         7 . The semiconductor devise according to  claim 1 , wherein
 the data transmitting circuit transmits a strobe signal, the strobe signal corresponding to and being in synchronization with the transmission data.   
     
     
         8 . The semiconductor devise according to  claim 1 , wherein
 the data transmitting circuit transmits the transmission data and the strobe signal after outputting a command for data transmission.   
     
     
         9 . The semiconductor devise according to  claim 1 ,
 further comprising a data receiving circuit that receives the transmission data, wherein the data receiving circuit receives the transmission data in synchronization with the strobe signal.