Controlling distributed power stages responsive to the activity level of functions in an integrated circuit

Abstract

A method includes obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

What is claimed is: 
     
         1 . A method, comprising:
 obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit; and   dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.   
     
     
         2 . The method of  claim 1 , wherein the amount of current supplied by each power stage is dynamically adjusted to reduce power losses between the power stages and the functions relative to an amount of power losses that would occur if each power stage provided an equal amount of current. 
     
     
         3 . The method of  claim 1 , wherein the amount of current supplied by each power stage is dynamically adjusted to minimize power losses between the power stages and the functions. 
     
     
         4 . The method of  claim 1 , wherein the amount of current supplied by each power stage is weighted according to the activity level of a function closest to each power stage. 
     
     
         5 . The method of  claim 1 , wherein the integrated circuit is rectangular and the plurality of power stages are located on at least two opposing sides of the integrated circuit. 
     
     
         6 . The method of  claim 5 , wherein the plurality of functions includes at least four functions and the plurality of power stages includes at least four power stages. 
     
     
         7 . The method of  claim 6 , wherein at least one of the power stages is directly adjacent each one of the functions. 
     
     
         8 . The method of  claim 6 , wherein the plurality of power stages includes six power stages distributed around the perimeter of the integrated circuit, wherein there are two power stages located on each of three sides of the integrated circuit. 
     
     
         9 . The method of  claim 1 , wherein the activity level of each function is updated continuously during operation of the integrated circuit. 
     
     
         10 . The method of  claim 9 , further comprising:
 an internal controller of the integrated circuit communicating the activity level to a regulator controller over a control line or bus, wherein the regulator controller controls each of the power stages.   
     
     
         11 . The method of  claim 9 , wherein the amount of current provided by each power stage is dynamically controlled in response to the updated activity level for each function. 
     
     
         12 . The method of  claim 1 , wherein the plurality of functions are processor cores. 
     
     
         13 . The method of  claim 1 , further comprising:
 calculating the power losses between the power stages and the functions as the sum of the power loss between each power stage and each function, wherein the power loss is a function of the square of the amount of current multiplied by the electrical resistance in a conduction path from the power stage to the function.   
     
     
         14 . The method of  claim 13 , wherein the electrical resistance in the conduction path is a function of electrical resistivity of the conduction path and a path length of the conduction path. 
     
     
         15 . The method of  claim 14 , further comprising:
 storing a known path length or electrical resistance for each possible pairing of one of the functions and one of the power stages.   
     
     
         16 . The method of  claim 1 , wherein the plurality of functions includes a first function having an activity level that is greater than an activity level of the other functions, wherein the plurality of power stages includes a first power stage that is closest to the first function, and wherein the step of dynamically adjusting an amount of current provided to the integrated circuit by each of a plurality of power stages of a DC voltage regulator includes causing the first power stage to supply a greater than equal portion of the amount of current provided to the integrated circuit. 
     
     
         17 . The method of  claim 1 , further comprising:
 measuring the activity level of each function of the integrated circuit by way of a counter, a task size, or a processor sleep state.   
     
     
         18 . The method of  claim 1 , further comprising:
 determining a future activity level of a function by analyzing a queue of pending workload.   
     
     
         19 . The method of  claim 1 , further comprising:
 accessing a fixed lookup table that identifies an amount of current for each power stage for a particular activity level of each function.   
     
     
         20 . The computer program product of  claim 1 , wherein each power stage supplies electrical current to a power plane and each function is electrically connected between the power plane and a ground plane, and wherein the power losses between the power stages and the functions occur in the power plane and the ground plane;
 the method further comprising:   calculating the power losses in the power and ground planes as the sum of the power loss between each power stage and each function, wherein the power loss is a function of the square of the amount of current multiplied by the electrical resistance in a current loop from the power stage to the function through the power plane and from the function to the power stage through the ground plane.