Chip package and method for forming the same

Abstract

An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

What is claimed is: 
     
         1 . A chip package, comprising:
 a semiconductor substrate having a first surface and a second surface;   a device region disposed in the semiconductor substrate;   a dielectric layer disposed on the first surface of the semiconductor substrate;   a conducting pad structure disposed in the dielectric layer and electrically connected to the device region;   a carrier substrate disposed on the dielectric layer; and   a conducting structure disposed on a lower surface of the carrier substrate and electrically contacting with the conducting pad structure.   
     
     
         2 . The chip package as claimed in  claim 1 , further comprising an optical element disposed on the second surface of the semiconductor substrate. 
     
     
         3 . The chip package as claimed in  claim 2 , wherein the optical element comprises a light filter film, a microlens, or combinations thereof. 
     
     
         4 . The chip package as claimed in  claim 2 , further comprising a transparent substrate disposed on the second surface of the semiconductor substrate. 
     
     
         5 . The chip package as claimed in  claim 4 , further comprising a spacer layer disposed between the second surface of the semiconductor substrate and the transparent substrate. 
     
     
         6 . The chip package as claimed in  claim 1 , wherein the second surface of the semiconductor substrate is a substantially planar surface. 
     
     
         7 . The chip package as claimed in  claim 1 , further comprising a hole located in the carrier substrate, wherein the hole exposes the conducting pad structure, and the conducting structure extends into the hole to electrically contact with the conducting pad structure. 
     
     
         8 . A method for forming a chip package, comprising:
 providing a semiconductor substrate having a first surface and a second surface, wherein a device region is formed in the semiconductor substrate;   disposing a dielectric layer and a conducting pad structure on the first surface of the semiconductor substrate, wherein the conducting pad structure is located in the dielectric layer and completely covered by the dielectric layer;   bonding a carrier substrate on the dielectric layer; and   forming a conducting structure on a lower surface of the carrier substrate, wherein the conducting structure electrically contacts with the conducting pad structure.   
     
     
         9 . The method for forming a chip package as claimed in  claim 8 , further comprising thinning the semiconductor substrate from the second surface of the semiconductor substrate. 
     
     
         10 . The method for forming a chip package as claimed in  claim 8 , further comprising removing a portion of the carrier substrate and a portion of the dielectric layer to form a hole exposing the conducting pad structure, wherein the conducting structure extends from the lower surface of the carrier substrate into the hole to electrically contact with the conducting pad structure. 
     
     
         11 . The method for forming a chip package as claimed in  claim 8 , further comprising disposing an optical element on the second surface of the semiconductor substrate. 
     
     
         12 . The method for forming a chip package as claimed in  claim 11 , wherein the optical element comprises a light filter film, a microlens, or combinations thereof. 
     
     
         13 . The method for forming a chip package as claimed in  claim 8 , further
 disposing a spacer layer on the second surface of the semiconductor substrate; and   disposing a transparent substrate on the spacer layer.   
     
     
         14 . The method for forming a chip package as claimed in  claim 8 , not comprising removing a portion of the dielectric layer from a surface of the dielectric layer away from the semiconductor substrate such that the conducting pad structure is exposed before the step of bonding the carrier substrate is performed.