Integrated circuit product comprised of multiple p-type semiconductor devices with different threshold voltages

Abstract

Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

What is claimed: 
     
         1 . An integrated circuit product, comprising:
 a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only said second PMOS active region has a silicon germanium layer formed thereon;   a first PMOS device formed in and above said first PMOS active region, said first PMOS device having a first gate structure; and   a second PMOS device formed in and above said second PMOS active region, said second PMOS device having a second gate structure disposed on said silicon germanium layer.   
     
     
         2 . The product of  claim 1 , whereas, as between said first and second PMOS active regions, the product further comprises halo regions positioned only in said second PMOS active region and said first PMOS region is free of halo regions. 
     
     
         3 . The product of  claim 2 , wherein said first PMOS device is of an HVT type device and said second PMOS device is of one of an LVT type device and an RVT type device. 
     
     
         4 . The product of  claim 1 , wherein said first PMOS active region comprises first halo regions positioned therein with a first dopant concentration and said second PMOS active region has second halo regions positioned therein with a second dopant concentration formed therein, said first dopant concentration being substantially smaller than said second dopant concentration. 
     
     
         5 . The product of  claim 4 , wherein a ratio of said second dopant concentration to said first dopant concentration is at least about 2. 
     
     
         6 . The product of  claim 4 , wherein said first PMOS device is of an SHVT type device and said second PMOS device is of one of an RVT type device and an LVT type device. 
     
     
         7 . The product of  claim 1 , wherein said first PMOS device represents one of an HVT and an SHVT type device and said second PMOS device represents one of an LVT and an RVT type device. 
     
     
         8 . The product of  claim 1 , wherein said first PMOS active region is free of any halo regions. 
     
     
         9 . The product of  claim 8 , wherein said first PMOS active region comprises only P-type doped regions. 
     
     
         10 . The product of  claim 1 , wherein said first gate structure comprises a gate insulation layer and a gate electrode. 
     
     
         11 . The product of  claim 1 , wherein said second gate structure comprises a gate insulation layer and a gate electrode. 
     
     
         12 . An integrated circuit product, comprising:
 a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only said second PMOS active region has a silicon germanium layer formed thereon;   a first PMOS device formed in and above said first PMOS active region, said first PMOS device having a first gate structure comprising a high-k gate insulation layer and a gate electrode;   a second PMOS device formed in and above said second PMOS active region, said second PMOS device having a second gate structure disposed on said silicon germanium layer, said second gate structure comprising a high-k gate insulation layer and a gate electrode; and   N-type halo regions positioned only in said second PMOS active region while said first PMOS active region is free of N-type halo regions.   
     
     
         13 . The product of  claim 12 , wherein said first PMOS device is of an HVT type device and said second PMOS device is of one of an LVT type device and an RVT type device. 
     
     
         14 . The product of  claim 12 , wherein said first PMOS device represents one of an HVT and an SHVT type device and said second PMOS device represents one of an LVT and an RVT type device. 
     
     
         15 . The product of  claim 12 , wherein said first PMOS active region comprises only P-type doped regions. 
     
     
         16 . An integrated circuit product, comprising:
 a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only said second PMOS active region has a silicon germanium layer formed thereon;   a first PMOS device formed in and above said first PMOS active region, said first PMOS device having a first gate structure comprising a high-k gate insulation layer and a gate electrode;   a second PMOS device formed in and above said second PMOS active region, said second PMOS device having a second gate structure disposed on said silicon germanium layer, said second gate structure comprising a high-k gate insulation layer and a gate electrode;   first N-type halo regions positioned in said first PMOS active region, said first N-type halo regions having a first dopant concentration; and   second N-type halo regions positioned in said second PMOS active region, said second N-type halo regions having a second dopant concentration, wherein said first dopant concentration is substantially smaller than said second dopant concentration.   
     
     
         17 . The product of  claim 16 , wherein a ratio of said second dopant concentration to said first dopant concentration is at least about 2.