Content addressable memory

Abstract

The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

What is claimed is: 
     
         1 . A content addressable memory, comprising:
 a memory array having a plurality of match lines, a plurality of search lines, and a plurality of memory cells, each of the memory cells coupled to a corresponding one of the match lines and a corresponding pair of the search lines;   a search control circuit generating a search line enable signal, and being coupled to a control signal line through which the search line enable signal is transmitted;   a plurality of search line drivers, each of the search line drivers being coupled to the control signal line and being provided to drive the corresponding pair of the search lines based on search data, when an asserted search line enable signal is received; and   a plurality of precharge units, each of the precharge units being provided to precharge a corresponding one of the match lines, wherein   the search control circuit further generates a match line precharge signal for activating the precharge units after a predetermined period of time from when the search line enable signal is de-asserted,   the predetermined period of time is determined by a wiring delay of the control signal line.   
     
     
         2 . The content addressable memory according to  claim 1 , further comprises a plurality of match amplifiers, each of the match amplifiers being provided to detect logic level of the corresponding one of the match lines,
 wherein the search control circuit further generates a match amplifier control signal for activating the match amplifiers after the predetermined period of time from when search line enable signal is de-asserted.   
     
     
         3 . The content addressable memory according to  claim 2 , wherein
 each of the match amplifier includes:
 a comparator configured to compare a voltage of the corresponding one of the match lines with a voltage of a reference match line; and 
 a transfer gate between the corresponding one of the match lines and the comparator, and 
   the comparator or the transfer gate are activated in response to the match amplifier control signal.