US2015381393A1PendingUtilityA1

Adaptive Cancellation of Voltage Offset in a Communication System

Assignee: LSI CORPPriority: Sep 13, 2011Filed: Jun 26, 2014Published: Dec 31, 2015
Est. expirySep 13, 2031(~5.1 yrs left)· nominal 20-yr term from priority
H04L 25/03057H04L 7/0331H04L 25/03885H04L 25/0292H04L 25/0307H04L 2025/037H04L 2025/03636H04L 25/03159H04L 7/033
51
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Claims

exact text as granted — not AI-modified
1 . A receiver having an input, the receiver comprising:
 an analog front end coupled to the receiver input and having an output;   a first subtractor having a first input coupled to the output of the analog front end and having an output;   a slicer coupled to the output of the first subtractor and having an output;   a multiplier having an output, a first input coupled to the output of the slicer; and a second input adapted to receive a weighting factor;   a second subtractor having an output, a first input coupled to the output of the multiplier, and a second input, coupled to the input of the slicer; and   an offset adaptation controller having an input coupled to the output of the second subtractor and configured to produce at an output a signal coupled to a second input of the first subtractor.   
     
     
         2 . The receiver of  claim 1  further comprising a sampler disposed between the output of the second subtractor and the input of the slicer. 
     
     
         3 . The receiver of  claim 1  wherein the weighting factor is a signal proportional to an amplitude of signals applied to the input of the receiver. 
     
     
         4 . The receiver of  claim 1  further comprising another slicer disposed between the output of the second subtractor and the input of the offset adaptation controller. 
     
     
         5 . The receiver of  claim 1  further comprising:
 a third subtractor having a first input coupled to the output of the first subtractor, a scoop input, and an output; and 
 a decision feedback equalizer having an output and at least one tap coefficient and coupled to the output of the slicer; 
 wherein the output of the decision feedback equalizer is coupled to the second input of the third subtractor. 
 
     
     
         6 . The receiver of  claim 5  further comprising a feed-forward equalizer disposed between the output of the first subtractor and the first input of the third subtractor. 
     
     
         7 . The receiver of  claim 6  further comprising:
 a decision feedback equalizer adaptation controller coupled to the output of the slicer and the output of the second subtractor; 
 wherein the decision feedback equalizer adaptation controller generates the weighting factor and controls the decision feedback equalizer, the feed-forward equalizer, and the analog front end. 
 
     
     
         8 . The receiver of  claim 7  wherein the decision feedback equalizer adaptation controller and the offset adaptation controller are one controller. 
     
     
         9 . The receiver of claim wherein the offset adaptation controller is configured to perform the following steps:
 read the input of the offset adaptation controller to generate a gradient;   calculate a offset value based on a past offset value adjusted by a combination of the gradient and a step size; and   output to the output of the offset adaptation controller the calculated offset value.   
     
     
         10 . The receiver of  claim 9  wherein the steps are repeated. 
     
     
         11 . The receiver of  claim 9  wherein the analog front end has a DC offset and the step size is substantially determined by a range of the DC offset divided by a desired number of steps. 
     
     
         12 . The receiver of  claim 11  wherein the step size ranges from approximately 10 −6  to approximately 10 −2  V/step. 
     
     
         13 . The receiver of  claim 1  wherein the receiver is implemented in an integrated circuit. 
     
     
         14 .- 26 . (canceled) 
     
     
         27 . In a system including a receiver, the receiver having an input and an analog front end coupled to the input, a method comprising:
 applying an input signal to the receiver input, the input signal having an amplitude level;   filtering the applied input signal with analog front-end circuitry;   subtracting from the filtered input signal an offset cancelation value to form a compensated signal;   slicing the compensated signal;   generating an error signal based on the sliced compensated signal and a weighting factor; and   calculating the offset cancelation value based sari a past offset cancelation value adjusted by a combination of the error signal and a step size;   wherein the weighting factor is proportional to the amplitude level.   
     
     
         28 . The method of  claim 27  further comprising the step of:
 slicing the error signal; 
 wherein the step of calculating the offset cancelation value is adjusted based on the sliced error signal. 
 
     
     
         29 .- 32 . (canceled) 
     
     
         33 . The method of  claim 27  wherein the step of generating an error signal based on the sliced compensated signal and a weighting factor comprises the step of:
 multiplying the sliced compensated signal by the weighting factor.

Join the waitlist — get patent alerts

Track US2015381393A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.