Semiconductor device

Abstract

The present invention is directed to solve a problem that, in a semiconductor device capable of generating a clock signal by coupling a quartz oscillator to an external terminal to which an I/O port is coupled, leak current of the I/O port which is in the inactive state disturbs activation of a clock. The semiconductor device has a first terminal, an amplification circuit coupled to the first terminal, and an output buffer whose output terminal is coupled to the first terminal. The output buffer has first and second transistors of a first conduction type coupled in series via a first node between a first power supply line and an output terminal, and the conduction states of the first and second transistors of the first conduction state are controlled in response to a first control signal which is applied commonly to the gate of each of the first and second transistors.

1 - 14 . (canceled) 
     
     
         15 . A semiconductor device comprising:
 a first terminal and a second terminal for coupling to a quartz oscillator;   an inverter circuit;   a resistor electrically coupled between the first and second terminal; and   a first output buffer coupled to the first terminal and outputting an input signal to the first terminal,   wherein an input terminal of the inverter circuit is electrically connected to the first terminal and an output terminal of the inverter circuit is electrically connected to the second terminal, and   wherein the first output buffer has a first p-type transistor whose source is coupled to a first power supply line for supplying power supply voltage, a second p-type transistor whose source is coupled to drain of the first p-type transistor and whose drain is coupled to the first terminal, a first n-type transistor whose source is coupled to a second power supply line which supplies ground voltage, and a second n-type transistor whose source is coupled to the drain of the first n-type transistor and whose drain is coupled to the first terminal.   
     
     
         16 . The semiconductor device according to  claim 15 , wherein the first output buffer further includes a first electric path different from the first and second n-type transistors formed between the drain of the first p-type transistor and the second power supply line, and a second electric path different from the first and second p-type transistors formed between the drain of the first n-type transistor and the first power supply line. 
     
     
         17 . The semiconductor device according to  claim 16 , wherein the first electric path is realized by a third n-type transistor whose drain is coupled to the drain of the first p-type transistor and whose source is coupled to the second power supply line, and the second electric path is realized by a third p-type transistor whose drain is coupled to the drain of the first n-type transistor and whose source is coupled to the first power supply line. 
     
     
         18 . The semiconductor device according to  claim 15 , further comprising a second output buffer coupled to the second terminal and outputting an input signal to the second terminal,
 wherein the second output buffer includes a third p-type transistor coupled to the first power supply line, a fourth p-type transistor whose source is coupled to the drain of the third p-type transistor and whose drain is coupled to the second terminal, a third n-type transistor whose source is coupled to the second power supply line, and a fourth n-type transistor whose source is coupled to the drain of the third n-type transistor and whose drain is coupled to the second terminal.   
     
     
         19 . The semiconductor device according to  claim 18 ,
 wherein the first output buffer further comprises a first electric path different from the first and second n-type transistors formed between the drain of the first p-type transistor and the second power supply line, and a second electric path different from the first and second p-type transistors formed between the drain of the first n-type transistor and the first power supply line, and   wherein the second output buffer further comprises a third electric path different from the third and fourth n-type transistors formed between the drain of the third p-type transistor and the second power supply line, and a fourth electric path different from the third and fourth p-type transistors formed between the drain of the third n-type transistor and the first power supply line.   
     
     
         20 . The semiconductor device according to  claim 19 ,
 wherein the first electric path is realized by a fifth n-type transistor whose drain is coupled to the drain of the first p-type transistor and whose source is coupled to the second power supply line,   wherein the second electric path is realized by a fifth p-type transistor whose drain is coupled to the drain of the first n-type transistor and whose source is coupled to the first power supply line,   wherein the third electric path is realized by a sixth n-type transistor whose drain is coupled to the drain of the third p-type transistor and whose source is coupled to the second power supply line, and   wherein the fourth electric path is realized by a sixth p-type transistor whose drain is coupled to the drain of the third n-type transistor and whose source is coupled to the first power supply line.