Resistive memory cell

Abstract

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.

1 - 20 . (canceled) 
     
     
         21 . A method of forming a resistive memory cell, comprising:
 forming a first dielectric region between two electrodes;   forming a barrier dielectric region on the first dielectric region; and   forming a second dielectric region on the barrier dielectric region,   wherein forming the barrier dielectric region includes forming a crystalline barrier dielectric region adjacent an amorphous first or second dielectric region, and wherein forming the barrier dielectric region includes forming an amorphous barrier dielectric region adjacent a crystalline first or second dielectric region.   
     
     
         22 . The method of  claim 21 , further comprising forming one or more additional instances of barrier dielectric regions and dielectric regions, wherein dielectric regions and additional instances of barrier dielectric regions alternate, and each additional instances of barrier dielectric region is located between dielectric regions. 
     
     
         23 . The method of  claim 21 , wherein forming the barrier dielectric region includes forming to a thickness of less than about 20 Angstroms. 
     
     
         24 . The method of  claim 21 , wherein forming the first and second dielectric regions includes forming the first and second dielectric regions to a thickness of between from about 10 to about 100 Angstroms. 
     
     
         25 . The method of  claim 21 , wherein the thickness of the first and second dielectric regions and the barrier dielectric region is between from about 50 to about 1000 Angstroms. 
     
     
         26 . The method of  claim 21 , wherein forming the first and second dielectric regions includes forming a first and second metal oxide region. 
     
     
         27 . The method of  claim 26 , wherein forming the first and second metal oxide regions includes forming a first and second amorphous metal oxide region. 
     
     
         28 . The method of  claim 26 , wherein forming the first and second metal oxide regions includes forming a first and second crystalline metal oxide region. 
     
     
         29 . The method of  claim 26 , wherein forming the first and second metal oxide regions includes forming at least one amorphous metal oxide region and at least one crystalline metal oxide region. 
     
     
         30 . The method of  claim 26 , wherein forming the first and second metal oxide regions includes forming at least one of a titanium dioxide (TiO 2 ) region, a lanthanum oxide (La 2 O 3 ) region, a gallium oxide (Ga 2 O 3 ) region, a zirconium oxide (ZrO 2 ) region, a zirconium silicon oxide (Zr X Si Y O Z ) region, a hafnium oxide (HfO 2 ) region, a hafnium silicon oxide (Hf X Si Y O Z ) region, and a strontium titanate (SrTiO 3 ) region. 
     
     
         31 . The method of  claim 21 , wherein forming the barrier dielectric region includes forming at least one of a silicon dioxide (SiO 2 ) region; an aluminum oxide (Al 2 O 3 ) region; a zirconium oxide (ZrO 2 ) region; and an amorphous doped silicon region. 
     
     
         32 . The method of  claim 21 , wherein forming the barrier dielectric region includes forming a material having a smaller grain size relative to a grain size of the first and second dielectric regions, the first and second dielectric regions being crystalline metal oxide materials. 
     
     
         33 . The method of  claim 21 , further comprising forming a buffer dielectric region between the electrode and the first dielectric region, wherein the buffer dielectric region has non-reactive stable electrical properties, and a lower k value and higher resistance than the first dielectric region. 
     
     
         34 . The method of  claim 21 , further comprising forming a buffer dielectric region between the electrode and the first dielectric region, wherein the buffer dielectric region has non-reactive stable electrical properties, and a higher k value and lower resistance than the first dielectric region. 
     
     
         35 . A method of forming a resistive memory cell, comprising:
 forming a first electrode of the resistive memory cell;   forming an alternating plurality of dielectric regions and plurality of barrier dielectric regions on the first electrode such that each is arranged to be substantially perpendicular to the first electrode, wherein each of the plurality of barrier dielectric regions is respectively located between dielectric regions; and   forming a second electrode of the resistive memory cell on, and subsequent to forming, the alternating plurality of dielectric regions and plurality of barrier dielectric regions, wherein the second electrode is arranged to be substantially parallel to the first electrode and each of the alternating plurality of dielectric regions and plurality of barrier dielectric regions formed between the first electrode of the resistive memory cell and the second electrode of the resistive memory cell are everywhere substantially perpendicular to the first electrode of the resistive memory cell and the second electrode of the resistive memory cell.   
     
     
         36 . The method of  claim 35 , wherein forming alternating dielectric region and barrier dielectric region on the first electrode of the resistive memory cell includes:
 forming a first dielectric region on the first electrode of the resistive memory cell such that the first dielectric region is arranged to have a substantially vertical orientation perpendicular to the first electrode of the resistive memory cell;   depositing a silicon dioxide barrier dielectric region on a sidewall of the first dielectric region;   forming the silicon dioxide barrier dielectric region to have a substantially vertical orientation perpendicular to the first electrode of the resistive memory cell;   depositing a second dielectric region on the formed silicon dioxide barrier dielectric region;   forming the second dielectric region to have a substantially vertical orientation perpendicular to the first electrode of the resistive memory cell.   
     
     
         37 . The method of  claim 35 , wherein forming alternating dielectric region and barrier dielectric region on the first electrode of the resistive memory cell includes:
 forming dielectric material on the first electrode of the resistive memory cell;   etching the dielectric material to form at least one trench substantially perpendicular to the first electrode of the resistive memory cell;   depositing a silicon dioxide barrier dielectric material into the at least one trench; and chemical-mechanical polishing (CMP) the dielectric and silicon dioxide barrier dielectric materials opposite the first electrode of the resistive memory cell.   
     
     
         38 . A method of forming a resistive memory cell, comprising:
 forming a number of dielectric regions formed between two electrodes; and   forming a barrier dielectric region between each of the dielectric regions, wherein the barrier dielectric region is:
 amorphous where the number of dielectric regions are crystalline; 
 crystalline where the number of dielectric regions are amorphous; and 
 wherein the barrier dielectric region is a grain-boundary disruptor relative to the number of dielectric regions. 
   
     
     
         39 . The method of  claim 38 , wherein forming the number of dielectric regions includes forming the number of dielectric regions to be amorphous. 
     
     
         40 . The method of  claim 38 , wherein the barrier dielectric region between each of the dielectric regions to has a slower oxygen diffusion rate relative to the number of dielectric regions.