Structure and method of forming silicide on fins

Abstract

Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET.

1 .- 16 . (canceled) 
     
     
         17 . A semiconductor structure, comprising
 a silicon substrate;
 a plurality of silicon fins formed in the silicon substrate; 
   an epitaxial region formed on a top portion of each of the plurality of fins, wherein the plurality of fins are unmerged; and   a silicide layer formed on, and substantially surrounding, each epitaxial region.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the silicide layer comprises nickel silicide. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein the plurality of fins have a pitch ranging from about 20 nanometers to about 60 nanometers. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein the plurality of fins each have a thickness ranging from about 5 nanometers to about 20 nanometers. 
     
     
         21 . The semiconductor structure of  claim 17 , further comprising a high-K dielectric layer on the silicon substrate adjacent to each fin of the plurality of fins. 
     
     
         22 . The semiconductor structure of  claim 21 , wherein the high-K dielectric layer comprises HfO2. 
     
     
         23 . The semiconductor structure of  claim 21 , wherein the high-K dielectric layer comprises ZrO2. 
     
     
         24 . The semiconductor structure of  claim 21 , further comprising an interlayer dielectric (ILD) formed on the high-K dielectric layer and a top portion of the silicide layer. 
     
     
         25 . The semiconductor structure of  claim 17 , wherein the silicide layer comprises tungsten silicide. 
     
     
         26 . A semiconductor structure, comprising
 a silicon substrate;
 a plurality of silicon fins formed in the silicon substrate; 
 a metal gate formed on the silicon substrate; 
   an epitaxial region formed on a top portion of each of the plurality of fins, wherein the plurality of fins are unmerged; and   a silicide layer formed on, and substantially surrounding, each epitaxial region.   
     
     
         27 . The semiconductor structure of  claim 25 , wherein the silicide layer comprises nickel silicide. 
     
     
         28 . The semiconductor structure of  claim 25 , wherein the silicide layer comprises tungsten silicide. 
     
     
         29 . The semiconductor structure of  claim 25 , wherein the plurality of fins have a pitch ranging from about 20 nanometers to about 60 nanometers. 
     
     
         30 . The semiconductor structure of  claim 25 , wherein the plurality of fins each have a thickness ranging from about 5 nanometers to about 20 nanometers. 
     
     
         31 . The semiconductor structure of  claim 25 , further comprising a high-K dielectric layer on the silicon substrate adjacent to each fin of the plurality of fins. 
     
     
         32 . The semiconductor structure of  claim 30 , wherein the high-K dielectric layer comprises HfO2. 
     
     
         33 . The semiconductor structure of  claim 30 , wherein the high-K dielectric layer comprises ZrO2. 
     
     
         34 . The semiconductor structure of  claim 30 , further comprising an interlayer dielectric (ILD) formed on the high-K dielectric layer and a top portion of the silicide layer. 
     
     
         35 . The semiconductor structure of  claim 25 , further comprising a nitride cap on the top and sides of the metal gate.