US2015380382A1PendingUtilityA1

Semiconductor device and method of manufacturing semiconductor device

Assignee: RENESAS ELECTRONICS CORPPriority: Feb 29, 2012Filed: Sep 10, 2015Published: Dec 31, 2015
Est. expiryFeb 29, 2032(~5.6 yrs left)· nominal 20-yr term from priority
H10W 95/00H10W 90/724H10W 72/9415H10W 72/07253H10W 72/07236H10W 72/01255H10W 72/01235H10W 72/952H10W 72/951H10W 72/923H10W 72/255H10W 72/252H10W 72/248H10W 72/242H10W 72/241H10W 72/234H10W 72/222H10W 72/0198H10W 72/072H10W 72/29H10W 90/701H10W 70/66H10W 20/032H01L 2924/01028H01L 23/49866H01L 24/81H01L 2224/13611H01L 2224/13147H01L 2224/81801H01L 2224/81191H01L 2924/2064H01L 2224/81385H01L 2924/014
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Claims

Abstract

A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device comprising:
 mounting a semiconductor chip in an interconnect substrate in a flip-chip manner,   wherein the semiconductor chip includes:   an electrode pad,   a Cu pillar, formed over the electrode pad, of which an upper surface is formed in a convex shape, and   a solder layer, formed over the Cu pillar, which contains Sn,   the interconnect substrate is made of a metal containing Cu, and includes a connection terminal connected to the solder layer,   a Ni layer is formed either between the Cu pillar and the solder layer or between the solder layer and the connection terminal, and   a minimum value of a thickness of the solder layer is equal to or less than 20 μm.   
     
     
         2 . The method of  claim 1 , wherein the Ni layer is formed in one of an interface between the Cu pillar and the solder layer and an interface between the solder layer and the connection terminal, and is not formed on another interface, and a thickness of a most thinnest part of the solder layer is equal to or less than 20 μm and equal to or more than 5 μm. 
     
     
         3 . The method of  claim 1 , wherein the solder layer includes an alloy layer of Cu and Sn, and at least a portion of the Cu pillar and at least a portion of the connection terminal are connected to each other through the alloy layer. 
     
     
         4 . The method of  claim 1 , wherein the solder layer includes an alloy layer of Cu and Sn, and the alloy layer grows as a current is caused to flow between the electrode pad and the connection terminal, so that at least a portion of the Cu pillar and at least a portion of the connection terminal are connected to each other through the alloy layer. 
     
     
         5 . The method of  claim 3 , wherein the alloy layer includes a Cu Sn 5  layer. 
     
     
         6 . The method of  claim 5 , wherein the alloy layer includes a Ni 3 Sn layer in an interface with the Ni layer, and includes a Cu 3 Sn layer in an interface with a layer of an one, in which the Ni layer is not formed, between the Cu pillar and the connection terminal. 
     
     
         7 . The method of  claim 1 , wherein a minimum value of a thickness of the solder layer is equal to or less than 15 μm. 
     
     
         8 . The method of  claim 1 , wherein a minimum value of a thickness of the solder layer is equal to or less than 12 μm. 
     
     
         9 . The method of  claim 1 , wherein a height of the convex shape is equal to or more than 5 μm and equal to or less than 10 μm.

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