Memory system

Abstract

According to one embodiment, there is provided a memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

1 - 20 . (canceled) 
     
     
         21 . A memory system comprising:
 a non-volatile memory device which stores data; and   a controller which monitors a characteristic of the non-volatile memory device and which controls a writing/erasing process of the non-volatile memory device,   wherein the writing/erasing process includes a plurality of writing/erasing loops,   each writing/erasing loop includes a writing/erasing operation and a verification operation to verify the writing/erasing operation,   the non-volatile memory device performs, in a first writing/erasing loop among the plurality of writing/erasing loops, the writing/erasing operation at a writing/erasing voltage which is set at a start value by the controller, and   the non-volatile memory device performs, in subsequent writing/erasing loops among the plurality of writing/erasing loops, the writing/erasing operation at the writing/erasing voltage which is incremented by an incremental amount by the controller,   and wherein the controller changes at least one of the start value and the incremental amount based on the monitored characteristic of the non-volatile memory device so that a time length necessary for the writing/erasing process is substantially equal to a target value.   
     
     
         22 . The memory system according to  claim 21 , wherein
 the monitored characteristic of the non-volatile memory device includes at least one of a frequency of the writing/erasing process, the time length necessary for the writing/erasing process, a number of the writing/erasing loops included in the writing/erasing process.   
     
     
         23 . The memory system according to  claim 21 , wherein
 the controller determines a variation degree from an initial state of characteristic of the non-volatile memory device based on the monitored characteristic, and changes, regarding the writing/erasing process, at least one of the value of the start value and the incremental amount so that variation amount corresponding to the determined variation degree of the time length necessary for the writing/erasing process can be canceled.   
     
     
         24 . The memory system according to  claim 23 , wherein
 the controller changes the start value to a first value and/or changes the incremental amount to be a first amount when the variation degree is a first degree, and changes the start value to a second value lower than the first value and/or changes the incremental amount to be a second amount smaller than the first amount when the variation degree is a second degree corresponding larger variation amount than the first degree.   
     
     
         25 . The memory system according to  claim 21 , wherein
 the controller changes either one of the start value or the incremental amount based on the monitored characteristic of the non-volatile memory device so that the time necessary for the writing/erasing process is substantially equal to the target value.   
     
     
         26 . The memory system according to  claim 21 , wherein
 the controller changes both the start value and the incremental amount based on the monitored characteristic of the non-volatile memory device so that the time necessary for the writing/erasing process is substantially equal to the target value.   
     
     
         27 . The memory system according to  claim 21 , wherein
 the controller further changes a verification voltage of the verification operation based on the monitored characteristic of the non-volatile memory device so that the time necessary for the writing/erasing process is substantially equal to the target value.   
     
     
         28 . A memory system comprising:
 a non-volatile memory device; and   a controller which sets, among a plurality of writing operations to the non-volatile memory device which are repeated with a verification operation for a first time length, a first voltage value to be used in a first writing operation and a second voltage value to be used in a second writing operation following the first writing operation,   the controller being configured to control at least either one of the first voltage value and a width between the first voltage value and the second voltage value and to be able to suppress changes in the first time length.   
     
     
         29 . The memory system according to  claim 28 , wherein
 the controller monitors a characteristic of the non-volatile memory device and controls at least either one of the first voltage value and the width.   
     
     
         30 . The memory system according to  claim 28 , wherein
 the controller changes at least one of the first voltage value and the width based on the monitored characteristic of the non-volatile memory device so that a time length necessary for the plurality of writing operations is substantially equal to a target value.   
     
     
         31 . A memory system comprising:
 a non-volatile memory device which stores data;   a controller which monitors a characteristic of the non-volatile memory device and which controls a writing/erasing process of the non-volatile memory device,   wherein the writing/erasing process includes a plurality of writing/erasing loops,   each writing/erasing loop includes a writing/erasing operation and a verification operation to verify the writing/erasing operation,   the non-volatile memory device performs, in a first writing/erasing loop among the plurality of writing/erasing loops, the writing/erasing operation at a writing/erasing voltage which is set at a start value by the controller, and   the non-volatile memory device performs, in subsequent writing/erasing loops among the plurality of writing/erasing loops, the writing/erasing operation at the writing/erasing voltage which is incremented by an incremental amount by the controller,   and wherein the controller changes a type of the verification operation from a first verification type to a second verification type based on the monitored characteristic of the non-volatile memory device.   
     
     
         32 . The memory system according to  claim 31 , wherein
 the first verification type includes an operation where a verification operation is performed at a second verification voltage,   the second verification type includes an operation where a verification operation is performed in two steps at a first verification voltage and at the second verification voltage, the first verification voltage being lower than the second verification voltage.   
     
     
         33 . The memory system according to  claim 31 , wherein
 the controller changes at least one of a level of the first verification voltage and a charging voltage of a bit line in the second verification type based on the monitored characteristic of the non-volatile memory device so that the time necessary for the writing/erasing process is substantially equal to a target value.   
     
     
         34 . The memory system according to  claim 33 , wherein
 the controller determines a variation degree from an initial state of characteristic of the non-volatile memory device based on the monitored characteristic, and changes, regarding the writing/erasing process, at least one of the level of the first verification voltage and the charging voltage of the bit line in the second verification type in response to a result of the determination so that variation amount corresponding to the determined variation degree of the time length necessary for the writing/erasing process can be canceled.   
     
     
         35 . The memory system according to  claim 33 , wherein
 the controller changes the level of the first verification voltage in the second verification type based on the monitored characteristic of the non-volatile memory device so that the time length necessary for the writing/erasing process is substantially equal to the target value.   
     
     
         36 . The memory system according to  claim 33 , wherein
 the controller changes the charging voltage of the bit line in the second verification type in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing/erasing process is substantially equal to the target value.   
     
     
         37 . The memory system according to  claim 33 , wherein
 the controller changes both the level of the first verification voltage and the charging voltage of the bit line in the second verification type in accordance with the monitored characteristic of the non-volatile memory device so that the time for the writing process is substantially equal to the target value.   
     
     
         38 . A memory system comprising:
 a non-volatile memory device; and   a controller which sets, among a plurality of writing operations to the non-volatile memory device which are repeated with a verification operation for a first time length, a first voltage value to be used in a first writing operation and a second voltage value to be used in a second operation following the first writing operation,   the controller being configured to refer to a characteristic of the non-volatile memory device and to be able to change a type of the verification operation.   
     
     
         39 . The memory system according to  claim 38 , wherein
 the controller changes the type of the verification operation from a first verification type to a second verification type based on the monitored characteristic of the non-volatile memory device.   
     
     
         40 . The memory system according to  claim 39 , wherein
 the first verification type includes an operation where a verification operation is performed at a second verification voltage,   the second verification type includes an operation where a verification operation is performed in two steps at a first verification voltage and at the second verification voltage, the first verification voltage being lower than the second verification voltage.