Semiconductor chip carriers with monolithically integrated quantum dot devices and method of manufacture thereof

Abstract

A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.

What is claimed is: 
     
         1 . A three-dimensional polycrystalline semiconductor material, comprising:
 a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm; and   a minor ingredient forming boundaries between the individual crystalline grains.   
     
     
         2 . The material of  claim 1 , wherein the minor ingredient surrounds the crystalline grains of the major ingredient. 
     
     
         3 . The material of  claim 1 , wherein quantum size effects within the polycrystalline material induce a free electron gas characteristic of a quantum well. 
     
     
         4 . The material of  claim 3 , wherein the polycrystalline material forms a three-dimensional quantum well structure. 
     
     
         5 . The material of  claim 1 , wherein the molar concentrations of the minor ingredient are between 0.0001 mol % and 0.75 mol % of the polycrystalline material. 
     
     
         6 . The material of  claim 1 , wherein the major ingredient comprising the crystalline grains is silicon, germanium, tin, or any admixture thereof. 
     
     
         7 . The material of  claim 6 , wherein the minor ingredient forming the grain boundaries is an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or an alkaline earth element from second (II) column of the periodic table, or a transition-metal having chemical properties similar to an alkali or alkaline earth metal, and a halogen element selected from the seventh (VII) column of the periodic table. 
     
     
         8 . The material of  claim 7 , wherein the insulating or semi-insulating material has an energy band gap that is larger than the band gap of the semiconductor material comprising the polycrystalline grain. 
     
     
         9 . The material of  claim 1 , wherein the major ingredient comprising crystalline grains is a III-V compound semiconducting material and the minor ingredient forming the boundaries is an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or a transition-metal having chemical properties similar to an alkali metal, and a halogen element selected from the seventh (VII) column of the periodic table. 
     
     
         10 . The material of  claim 1 , wherein the major ingredient of the crystalline grains is a II-VI compound semiconductor and the minor ingredient forming the boundaries is silicon, silicon carbide, germanium, tin or an admixture thereof. 
     
     
         11 . The material of  claim 1 , wherein the polycrystalline material has a three dimensional size that is greater than 50 nm in every direction. 
     
     
         12 . The material of  claim 1 , wherein the polycrystalline material is monolithically integrated into an active device. 
     
     
         13 . The material of  claim 12 , wherein the active device is a field effect transistor, an opto-electronic device or a photonic device. 
     
     
         14 . A semiconductor carrier, comprising an active device including a semiconductor layer that is monolithically integrated into the semiconductor carrier and is comprised of a nanoscale polycrystalline assembly including semiconducting crystalline grains having maximal physical dimensions in the range of 20 nm to 50 nm that are enveloped by a grain boundary material that is 2 nm to 10 nm thick, such that the quantum size effects within the polycrystalline grain induce a free electron gas characteristic of a quantum well. 
     
     
         15 . The semiconductor carrier of  claim 14 , wherein the active device is field effect transistor, an opto-electronic device or a photonic device. 
     
     
         16 . The semiconductor carrier of  claim 14 , wherein the active device comprises a power management module monolithically integrated on to its surface. 
     
     
         17 . The semiconductor carrier of  claim 14 , wherein the active device comprises a semiconductor die. 
     
     
         18 . The semiconductor carrier of  claim 14 , wherein the semiconductor carrier has active circuitry embedded within the carrier substrate. 
     
     
         19 . A method of fabricating a semiconductor layer comprised of a nanoscale polycrystalline assembly including semiconducting crystalline grains having maximal physical dimensions in the range of 20 nm to 50 nm that are enveloped by a grain boundary material that is 2 nm to 10 nm thick, such that the quantum size effects within the polycrystalline grain induce a free electron gas characteristic of a quantum well, comprising the following steps:
 forming a solution of low volatility liquid metalorganic precursors having stoichiometric ratios suitable for producing majority phase polycrystalline grains consisting of an elemental semiconductor or a desired compound semiconductor stoichiometry;   adding to said solution dopants in concentrations in the range of 0.0001 mol % to 0.5 mol % having stoichiometric ratios suitable for producing an insulating, semi-insulating, or semiconducting secondary phase material in the grain boundary of the majority phase polycrystalline grains;   adding to said solution precursors for the dopants to the majority phase polycrystalline grains in the concentrations desired within the polycrystalline grains;   heating a substrate upon which the semiconductor layer will be formed a temperature in the range of 250° C. to 500° C.;   simultaneously decomposing the non-volatile metalorganic precursors on the substrate in an inert or reducing gas atmosphere to form an amorphous deposit having stoichiometric precision that is chemically uniform at the atomic scale;   baking said amorphous deposit to remove organic residue from the deposit;   annealing said baked deposit for a minimum of 5 seconds in ionized argon plasma using an applied power of 50 W to 300 W at a substrate temperature between 40° C. and 400° C. and a pressure in the range of 1,500 mTorr to 5,000 mTorr; and   optionally adding nitrogen, and/or reducing partial pressure ratios of carbon dioxide and carbon monoxide to the ionized argon plasma.   
     
     
         20 . The method of  claim 19 , wherein the semiconducting material comprising the crystalline grains is silicon, germanium, tin, or any admixture thereof.