Semiconductor device with contacts and metal interconnects and method of manufacturing the semiconductor device

Abstract

A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a first interlayer insulation layer disposed over the substrate;   first transistors disposed over the substrate and buried in the first interlayer insulation layer;   a multilayered interconnect layer disposed over the first interlayer insulation layer, wherein a second interlayer insulation layer of the multilayered interconnect layer is disposed over the first interlayer insulation layer, and a third interlayer insulation layer of the multilayered interconnect layer is disposed over the second interlayer insulation layer;   capacitance devices disposed in the third interlayer insulation layer of the multilayered interconnect layer above the second interlayer insulation layer;   a gate electrode and a diffusion layer of each of the first transistors;   a metal interconnect in contact with the upper surface of the gate electrode, extended in a direction identical with the gate electrode and buried in the first interlayer insulation layer; and   first contacts coupled to the diffusion layer of the first transistor and buried in the first interlayer insulation layer, wherein the metal interconnect includes a material identical with that of the first contact;   second transistors disposed over the substrate and situated in a logic circuit region which is a region different from a memory circuit region including the first transistors;   a second contact for coupling the second transistor with a first interconnect;   wherein the metal interconnect includes a material identical with that of the first contact;   wherein the first interconnect is situated in the lowermost interconnect layer of the second interlayer insulation layer of the multilayered interconnect layer and extends entirely through the second interlayer insulation layer, the lowermost interconnect layer and the second contact being disposed below the capacitance devices,   wherein the second contact includes a material identical with that of the metal interconnect; and   bit lines situated in the memory circuit region, disposed in the layer identical with the first interconnect, and coupled to the diffusion layer of each of the first transistors, the bit lines arranged entirely below the capacitance devices and extending entirely through the second interlayer insulation layer,   wherein the metal interconnect includes a W-containing material, and   wherein the bit line includes a material identical with that of the first interconnect.   
     
     
         2 . The semiconductor device according to  claim 1 , comprising:
 a capacitance contact for coupling the first transistor and the capacitance device,   wherein the lower electrode of the capacitance device covers the upper surface and at least the upper portion of the lateral wall of the capacitance contact.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the capacitance contact has at least three or more contacts arranged in the direction of penetrating the interlayer.