Integrated circuit apparatus, three-dimensional integrated circuit, three-dimensional processor device, and process scheduler, with configuration taking account of heat

Abstract

The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately.

What is claimed is: 
     
         1 . The integrated circuit, comprising:
 one or more cache memories and one or more processor cores, characterized in that   the area of said cache memories is partitioned and laid-out into a plurality of circuit blocks in parallel to the direction perpendicular to one direction from the arranged position of said processor cores to the arranged position of said cache memories, on the circuit layout.   
     
     
         2 . A three-dimensional integrated circuit, comprising:
 a first chip and a second chip which is stacked on the first chip, characterized in that   the first chip comprises a circuit block with a relatively large heat value and a circuit block with a relatively small heat value,   the second chip comprises a circuit block with a relatively large heat value and a circuit block with a relatively small heat value, and   the positional relation between the first chip and the second chip at the superposition is adjusted and both are stacked so that the overlapping layered area of the circuit block with a relatively large heat value in the first chip and the circuit block with a relatively large heat value in the second chip is minimized.   
     
     
         3 . A three-dimensional integrated circuit made of two or more chips stacked, wherein
 at least two chips among the stacked chips have the same circuit block layout, and   the positional relation between the at least two chips at the superposition is adjusted and both are stacked so that the one circuit block layout does not overlap with the other.   
     
     
         4 . The three-dimensional integrated circuit according to  claim 3 , characterized in that
 one of the chips is stacked in the different orientations by 90 degrees or 180 degrees from the other chip in the at least two chips with the same circuit block layout.   
     
     
         5 . The three-dimensional integrated circuit according to  claim 3 , characterized in that
 the at least two chips with the same circuit block layout are processor chips forming a multi-core system.   
     
     
         6 . The three-dimensional integrated circuit in  claim 5 , characterized in that
 one of the processor chips is stacked in the different orientations by 90 degrees or 180 degrees from the other chip in the at least two processor chips.   
     
     
         7 . The three-dimensional integrated circuit according to  claim 5 , characterized in that
 each chip includes one or more processor cores and one or more level 2 cache memories,   a first area in which level 2 cache memories which are vertically adjacent to each other in stacking said chips is partitioned in each of the at least two processor chips, and   the partitioned first area is separately controlled in each of the processor chips.   
     
     
         8 . A three-dimensional processor device, comprising:
 a plurality of stacked processor chips and an assignment control unit, characterized in that   each processor chip has one or more processor cores,   the assignment control unit includes a processor core position storage unit which stores data on a position of each processor core in the three-dimensional processor device, and   the assignment control unit controls assignment of a program to each processor core based on the data on the position of each processor core stored in the processor core position storage unit.   
     
     
         9 . The three-dimensional processor device according to  claim 8 , characterized in that
 the assignment control unit controls the assignment of the program to each processor core so that the processor cores adjacently arranged in the vertical direction in the stacked processor chips do not execute the program at the same time.   
     
     
         10 . The three-dimensional processor device according to  claim 8 , characterized in that
 the assignment control unit controls to assign each program to the processor cores near to a heat sink on a priority basis in the stacked processor.