TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

Abstract

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

What is claimed is: 
     
         1 . A chip package comprising:
 a mold having a front side and a rear side;   a first set of electrical traces disposed on the front side of the mold;   a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the first set of electrical traces, the front face of the IC die having a first electrical contact pad disposed thereon that is in contact with the first set of electrical traces;   a rear-side metallization exposed on a rear face of the first IC die, wherein a portion of the rear-side metallization is exposed through the rear side of the mold; and   a first solder ball disposed on the exposed portion of the rear-side metallization.   
     
     
         2 . The chip package of  claim 1 , further comprising:
 a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the first set of electrical traces;   a second rear-side metallization disposed on a rear face of the second IC die, wherein a portion of the second rear-side metallization is exposed through the rear side of the mold;   and a second solder ball disposed on the exposed portion of the second rear-side metallization.   
     
     
         3 . The chip package of  claim 2 , wherein the first and second IC dies are of different types. 
     
     
         4 . The chip package of  claim 2 , wherein the second IC die has electrical contact pads disposed on the front faces thereof, and wherein the electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by the first set of electrical traces. 
     
     
         5 . The chip package of  claim 2 , further comprising:
 a first via formed in the mold that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first via is located on the rear side of the mold and a second end of the first via is located on the front side of the mold;   and at least a third solder ball disposed on the first end of the first via.   
     
     
         6 . The chip package of  claim 5 , wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a second set of electrical traces. 
     
     
         7 . The chip package of  claim 2 , wherein the second IC die is a silicon die, and wherein the chip package further comprises:
 a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die;   a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and   at least a third solder ball disposed on the first TSV electrical contact.   
     
     
         8 . The chip package of  claim 7 , wherein the second end of the first TSV is electrically connected to a second electrical contact pad disposed on the front face of the second IC die by an electrical trace in the first set of electrical traces. 
     
     
         9 . The chip package of  claim 1 , further comprising:
 an optical element located adjacent the front face of the first IC die.   
     
     
         10 . The chip package of  claim 9 , wherein the optical element is at least one of a refractive lens, a Fresnel lens, and a holographic element. 
     
     
         11 . A two-sided-access extended, or embedded, wafer-level ball grid array (TSA eWLB) assembly comprising:
 a TSA eWLB package comprising:
 a mold having a front side and a rear side, a redistribution layer disposed on front side of the mold, the redistribution layer including layers of metal patterned to form electrical traces, at least a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the redistribution layer, the front face of the first IC having at least a first electrical contact pad disposed thereon that is in contact with the redistribution layer, a metal pattern disposed on a rear face of the first IC die and exposed through the rear side of the mold, the rear face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the metal pattern, and a first solder ball disposed on the exposed portion of the metal pattern; and 
 a printed circuit board (PCB) having an upper surface and a lower surface, the upper surface having electrical contacts disposed thereon, the TSA eWLB package being mounted on the upper surface of the PCB such that said at least a first solder ball of the TSA eWLB package is in contact with the one of the electrical contacts disposed on the upper surface of the PCB. 
   
     
     
         12 . The TSA eWLB assembly of  claim 11 , wherein the TSA eWLB package further comprises:
 a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the redistribution layer;   a second metal pattern disposed on a rear face of the second IC die, wherein a portion of the second metal pattern is exposed through the rear side of the mold; and   a second solder ball disposed on the exposed portion of the second metal pattern, and wherein the second solder ball is in contact with one of the electrical contacts disposed on the upper surface of the PCB.   
     
     
         13 . The TSA eWLB assembly of  claim 12 , wherein the first and second IC dies are of different types. 
     
     
         14 . The TSA eWLB assembly of  claim 12 , wherein the second IC die has at least a first electrical contact pad disposed on the front face thereof, and wherein the first electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by a first electrical trace of the redistribution layer. 
     
     
         15 . The TSA eWLB assembly of  claim 12 , wherein the TSA eWLB package further comprises:
 a first thru-mold via (TMV) formed in the mold, the first TMV comprising a hole that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first TMV is located on the rear side of the mold and a second end of the first TMV is located on the front side of the mold; and   a third solder ball disposed on the first end of the first TMV, the third solder ball being in contact with one of the electrical contacts disposed on the upper surface of the PCB.   
     
     
         16 . The TSA eWLB assembly of  claim 15 , wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a second electrical trace of the redistribution layer. 
     
     
         17 . The TSA eWLB assembly of  claim 12 , wherein the second IC die is a silicon die, and wherein the TSA eWLB package further comprises:
 at least a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die;   a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and   a third solder ball disposed on the first TSV electrical contact, the third solder ball being in contact with one of the electrical contacts disposed on the upper surface of the PCB.   
     
     
         18 . The TSA eWLB assembly of  claim 17 , wherein the second end of the first TSV is electrically connected to a second electrical contact pad disposed on the front face of the second IC die by a second electrical trace of the redistribution layer. 
     
     
         19 . The TSA eWLB assembly of  claim 12 , wherein the first IC die is an electrical-to-optical converter and the second IC die is an optical-to-electrical converter, and wherein the assembly further comprises:
 a cap secured to the front side of the mold, the cap having first and second optical pathways formed therein, the first and second optical pathways being located above the first and second IC dies, respectively, the first optical pathway directing light emitted by the first IC die in a direction that is away from the first IC die and generally normal to the front face of the first IC die, the second optical pathway directing light that falls onto the assembly and onto the second optical pathway in a direction that is toward the second IC die and generally normal to the front face of the second IC die.