Circuits incorporating integrated passive devices having inductances in 3d configurations and stacked with corresponding dies

Abstract

A circuit including: a die a first substrate and at least one active device; an integrated passive device including a first layer, a second substrate, a second layer and an inductance; and a third layer. The inductance includes vias and is an electrostatic discharge inductance. The vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars. The pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

What is claimed is: 
     
         1 . A circuit comprising:
 a die comprising a first substrate and at least one active device;   an integrated passive device comprising a first layer, a second substrate, a second layer and an inductance, wherein the inductance comprises a plurality of vias, wherein the inductance is an electrostatic discharge inductance, wherein the plurality of vias are implemented in the second substrate, wherein the inductance is implemented on the first layer, the second substrate, and the second layer, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and   a third layer disposed between the die and the integrated passive device, wherein the third layer comprises a plurality of pillars, wherein the plurality of pillars respectively connect ends of the inductance to the at least one active device, and   wherein the die, the integrated passive device and the third layer are disposed relative to each other to form a stack.   
     
     
         2 . The circuit of  claim 1 , wherein the inductance comprises:
 a first set of vias;   a second set of vias;   a first set of conductors implemented in the first layer and connecting the first set of vias respectively to the second set of vias; and   a second set of conductors implemented in the second layer and connecting the first set of vias respectively to the second set of vias.   
     
     
         3 . The circuit of  claim 2 , wherein:
 each of the second set of conductors comprises a first portion and a second portion;   the first portions extend parallel to each other and parallel to the first set of conductors; and   each of the second portions extend parallel to each other and do not extend parallel to the first set of conductors.   
     
     
         4 . The circuit of  claim 3 , wherein some of the first set of conductors extend between corresponding pairs of the second set of vias. 
     
     
         5 . The circuit of  claim 4 , wherein:
 the first set of conductors comprises first portions and second portions;   the second set of conductors comprises first portions and second portions;   the first portions of the first set of conductors and the first portions of the second set of conductors provide a first magnetic field;   the second portions of the first set of conductors and the second portions of the second set of conductors provide a second magnetic field; and   the first magnetic field extends perpendicular to the second magnetic field.   
     
     
         6 . A circuit comprising:
 a die comprising a first substrate and at least one active device;   an integrated passive device comprising a first layer, a second substrate, a second layer and a balun, wherein the balun comprises a first inductance, a second inductance, a plurality of loops, and a plurality of vias, wherein the plurality of vias are implemented in the second substrate, and wherein each of the plurality of loops is implemented on the first layer, the second substrate, and the second layer, wherein the plurality of loops comprises a first loop and a second loop, wherein the second loop is disposed within the first loop, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and   a third layer disposed between the die and the integrated passive device, wherein the third layer comprises a plurality of pillars, wherein the plurality of pillars respectively connect ends of the balun to the at least one active device, and   wherein the die, the integrated passive device and the third layer are disposed relative to each other to form a stack.   
     
     
         7 . The circuit of  claim 6 , wherein:
 the balun comprises a first set of conductors and a second set of conductors;   the plurality of vias comprise first vias and second vias;   the first inductance comprises the first vias and the first set of conductors; and   the second inductance comprises the second vias and the second set of conductors.   
     
     
         8 . The circuit of  claim 7 , wherein:
 the balun comprises a third loop and a fourth loop;   the first set of conductors comprises a first conductor and a second conductor;   the second set of conductors comprises a third conductor and a fourth conductor;   the first conductor provides the first loop;   the second conductor provides the third loop;   the third conductor provides the second loop;   the fourth conductor provides the fourth loop;   the first loop is stacked on the second loop;   the third loop is stacked on the fourth loop; and   the plurality of vias are disposed between the second loop and the third loop.   
     
     
         9 . The circuit of  claim 8 , wherein the second set of conductors overlap respectively the first set of conductors. 
     
     
         10 . The circuit of  claim 6 , wherein the balun is a stacked balun. 
     
     
         11 . The circuit of  claim 6 , wherein the balun is a double loop balun such that:
 every other loop of the first inductance is within every other loop of the second inductance; and   every other loop of the second inductance is within every other loop of the first inductance.   
     
     
         12 . The circuit of  claim 6 , wherein the plurality of loops are stacked, overlap each other, and are on respective layers of the integrated passive device. 
     
     
         13 . A circuit comprising:
 a die comprising a first substrate and at least one active device;   an integrated passive device comprising (i) a first layer, (ii) a second substrate, (iii) a second layer, and (iv) a plurality of inductances including a first inductance, a second inductance, a first crossover, and a second crossover, wherein the first inductance includes a first pair of conductors and a first plurality of vias, wherein the second inductance includes a second pair of conductors and a second plurality of vias, wherein the first pair of conductors, the second pair of conductors, the first plurality of vias and the second plurality of vias extend between the first crossover and the second crossover, wherein each of the first crossover and the second crossover are at ends of each of the first inductance and the second inductance, wherein the first plurality of vias and the second plurality of vias are implemented in the second substrate, and wherein the plurality of inductances are implemented on the first layer, the second substrate, and the second layer; and   a third layer disposed between the die and the integrated passive device, wherein the third layer comprises a plurality of pillars, wherein the plurality of pillars respectively connect the ends of the first inductance and the second inductance to the at least one active device, and   wherein the die, the integrated passive device and the third layer are disposed relative to each other to form a stack.   
     
     
         14 . The circuit of  claim 13 , comprising a directional coupler, wherein the directional coupler comprises the first inductance and the second inductance. 
     
     
         15 . The circuit of  claim 13 , comprising a balun, wherein the balun comprises the first inductance and the second inductance. 
     
     
         16 . The circuit of  claim 13 , wherein:
 the first crossover comprises a third pair of conductors;   the second crossover comprises a fourth pair of conductors;   each of the third pair of conductors connects one of the first plurality of vias to another one of the first plurality of vias; and   each of the fourth conductors connects one of the second plurality of vias to another one of the second plurality of vias.   
     
     
         17 . The circuit of  claim 13 , wherein:
 the first inductance includes a first portion of the first crossover and a first portion of the second crossover; and   the second inductance includes a second portion of the first crossover and a second portion of the second crossover.   
     
     
         18 . The circuit of  claim 13 , wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. 
     
     
         19 . The circuit of  claim 13 , wherein:
 the first plurality of vias comprise a first pair of vias and a second pair of vias;   the second plurality of vias comprise a third pair of vias and a fourth pair of vias;   the first pair of vias are connected to each other by the first crossover;   the third pair of vias are connected to each other by the first crossover;   the second pair of vias are connected to each other by the second crossover; and   the fourth pair of vias are connected to each other by the second crossover.   
     
     
         20 . The circuit of  claim 13 , wherein:
 the first pair of conductors comprise a first conductor and a second conductor;   the second pair of conductors comprises a third conductor and a fourth conductor;   the third conductor is disposed on the first conductor; and   the second conductor is disposed on the fourth conductor.