Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication

Abstract

Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

What is claimed is: 
     
         1 . A method for controlling microloading variation in a semiconductor wafer layout, comprising:
 defining a first layout that includes both permanent layout features and a number of sacrificial layout features;   fabricating structures corresponding to both the permanent layout features and the number of sacrificial layout features of the first layout in a target material layer on a wafer;   defining a second layout to remove structures corresponding to the number of sacrificial layout features; and   utilizing the second layout to remove the structures corresponding to the number of sacrificial layout features from the target material layer on the wafer.   
     
     
         2 . The method of  claim 1 , wherein the number of sacrificial layout features are defined and placed in the first layout to reduce adverse microloading variation effects and support fabrication of structures corresponding to the permanent layout features. 
     
     
         3 . The method of  claim 1 , wherein the number of sacrificial layout features are defined and placed to limit variation in size and relative location of open areas in the first layout. 
     
     
         4 . The method of  claim 1 , wherein the target material layer is formed of an electrically conductive material. 
     
     
         5 . The method of  claim 4 , wherein a portion of the structures corresponding to the permanent layout features of the first layout define gate electrodes of transistor devices. 
     
     
         6 . The method of  claim 1 , wherein the target material layer is formed of an electrically insulating material. 
     
     
         7 . The method of  claim 1 , wherein the second layout includes openings defined to uncover each of the number of sacrificial layout features fabricated in the target material layer. 
     
     
         8 . The method of  claim 7 , wherein the second layout also includes additional openings defined to uncover a number of segments of the permanent layout features fabricated in the target material layer to enable removal of the number of segments thereby cutting the permanent layout features. 
     
     
         9 . The method of  claim 1 , wherein the second layout is utilized in a subtractive etch process to remove the structures corresponding to the number of sacrificial layout features from the target material layer on the wafer. 
     
     
         10 . The method of  claim 1 , further comprising:
 splitting the first layout into a plurality of layouts to be used in a multiple patterning process, wherein each of the plurality of layouts includes a portion of the permanent layout features and a set of sacrificial layout features defined to control microloading variation among the portion of the permanent layout features, and   wherein fabricating structures corresponding to both the permanent layout features and the number of sacrificial layout features of the first layout in the target material layer on the wafer includes successively fabricating each of the plurality of layouts into which the first layout is split.   
     
     
         11 . The method of  claim 10 , wherein the set of sacrificial layout features is defined to limit variation in size and relative location of open areas in its layout. 
     
     
         12 . The method of  claim 1 , further comprising:
 recording the first and second layouts in a digital format on a computer readable medium.   
     
     
         13 . The method of  claim 12 , wherein the digital format is a data file format for storing and communicating one or more semiconductor device layouts. 
     
     
         14 . The method of  claim 12 , wherein the computer readable medium includes program instructions for accessing and retrieving the first and second layouts in the digital format from the computer readable medium. 
     
     
         15 . The method of  claim 14 , wherein the program instructions for accessing and retrieving include program instructions for selecting a library, a cell, or both library and cell including the first and second layouts in the digital format. 
     
     
         16 . A method for controlling microloading variation in a semiconductor wafer layout, comprising:
 identifying a first open area in a layout having a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation; and   repositioning a number of layout features within the layout so as to interdict the first open area such that the size variation of the first open area relative to the one or more neighboring open areas is reduced.   
     
     
         17 . The method of  claim 16 , wherein microloading variation is a variation in size and location of material areas to be etched from a semiconductor wafer. 
     
     
         18 . The method of  claim 17 , wherein the adverse microloading variation is an unacceptable variation in etch rate between different locations on the semiconductor wafer. 
     
     
         19 . The method of  claim 16 , wherein an open area in a layout is a space between layout shapes to be lithographically resolved during fabrication. 
     
     
         20 . The method of  claim 16 , further comprising:
 recording a layout including the repositioned layout features in a digital format on a computer readable medium.   
     
     
         21 . The method of  claim 20 , wherein the digital format is a data file format for storing and communicating one or more semiconductor device layouts. 
     
     
         22 . The method of  claim 20 , wherein the computer readable medium includes program instructions for accessing and retrieving the layout in the digital format from the computer readable medium. 
     
     
         23 . The method of  claim 22 , wherein the program instructions for accessing and retrieving include program instructions for selecting a library, a cell, or both library and cell including the layout in the digital format.