Stress inducing contact metal in finfet cmos

Abstract

A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer.

What is claimed is: 
     
         1 - 14 . (canceled) 
     
     
         15 . A semiconductor structure comprising;
 a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate;   a gate structure above a first portion of the first plurality of fins and a first portion of the second plurality of fins, the gate structure not covering a second portion of the first plurality of fins and a second portion of the second plurality of fins;   a first epitaxial layer surrounding the second portion of the first plurality of fins;   a second epitaxial layer surrounding the second portion of the second plurality of fins;   an ILD layer above the semiconductor substrate, the ILD layer covering the gate structure and separating the first region of the semiconductor substrate from the second region of the semiconductor substrate; and   a metal layer around the first epitaxial layer and above the top portion of the second epitaxial layer.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the first epitaxial layer surrounding the second portion of one fin in the first plurality of fins does not contact the first epitaxial layer surrounding an adjacent fin. 
     
     
         17 . The semiconductor structure of  claim 16 , wherein the second epitaxial layer surrounding the second portion of one fin in the second plurality of fins contacts the second epitaxial layer surrounding an adjacent fin. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein the second epitaxial layer surrounding the second portion of one fin in the second plurality of fins does not contact the second epitaxial layer surrounding an adjacent fin. 
     
     
         19 . The semiconductor structure of  claim 18 , wherein a portion of the ILD layer remains between the second epitaxial layer of one fin and the second epitaxial layer of an adjacent fin. 
     
     
         20 . The semiconductor structure of  claim 15 , wherein the metal layer applies stress to the first portion of the first plurality of fins.