Arrays Comprising Vertically-Oriented Transistors and Integrated Circuitry Comprising a Conductive Line Buried in Silicon-Comprising Semiconductor Material

Abstract

An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.

1 - 24 . (canceled) 
     
     
         25 . An array comprising vertically-oriented transistors, the array comprising rows of access lines and columns of data/sense lines, the array comprising:
 individual of the rows comprising an access line interconnecting transistors in that row; and   individual of the columns comprising a data/sense line interconnecting transistors in that column, the data/sense line comprising silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb, the conductively-doped semiconductor material of the data/sense line comprising a conductivity-neutral dopant between the transistors in that column.   
     
     
         26 . The array of  claim 25  wherein the conductivity-neutral dopant is at a concentration of from about 1×10 19  atoms/cm 3  to about 1×10 22  atoms/cm 3  where received in the silicon-comprising semiconductor material of the data/sense line. 
     
     
         27 . The array of  claim 25  wherein the n-type dopant is As. 
     
     
         28 . The array of  claim 25  wherein the n-type dopant is Sb. 
     
     
         29 . The array of  claim 25  wherein the conductivity-neutral dopant is carbon. 
     
     
         30 . The array of  claim 25  wherein the conductivity-neutral dopant is germanium. 
     
     
         31 . The array of  claim 25  wherein the conductivity-neutral dopant is continuously received along the individual data/sense lines. 
     
     
         32 . The array of  claim 31  wherein the continuously received conductivity-neutral dopant is homogenous along the individual data/sense lines. 
     
     
         33 . The array of  claim 25  further comprising another different conductivity-neutral dopant in silicon-comprising semiconductor material that is immediately elevationally inward of the data/sense lines. 
     
     
         34 . Integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material, the conductive line comprising the silicon-comprising semiconductor material that is conductively-doped n-type with at least one of As and Sb, the conductively-doped semiconductor material of the conductive line comprising a conductivity-neutral dopant. 
     
     
         35 . The array of  claim 25  wherein the data/sense lines are horizontally-oriented and individually have a thickness of from about 500 Angstroms to about 2,000 Angstroms. 
     
     
         36 . The array of  claim 25  wherein the n-type dopant is As and Sb. 
     
     
         37 . The array of  claim 25  wherein the conductivity-neutral dopant restricts to at least some degree vertical diffusion beyond the depth and/or height of a region of the silicon-comprising semiconductor material within which the conductivity-neutral dopant is received. 
     
     
         38 . The array of  claim 25  wherein the vertically-oriented transistors individually comprise part of a memory cell. 
     
     
         39 . The array of  claim 38  comprising a charge storage device that is electrically coupled to an elevationally outer source/drain region as part of the memory cell. 
     
     
         40 . The integrated circuitry of  claim 34  wherein the n-type dopant is As. 
     
     
         41 . The integrated circuitry of  claim 34  wherein the n-type dopant is Sb. 
     
     
         42 . The integrated circuitry of  claim 34  wherein the n-type dopant is As and Sb. 
     
     
         43 . The integrated circuitry of  claim 34  wherein the conductivity-neutral dopant is at a concentration of from about 1×10 19  atoms/cm 3  to about 1×10 22  atoms/cm 3  where received in the silicon-comprising semiconductor material of the data/sense line. 
     
     
         44 . The integrated circuitry of  claim 34  wherein the conductivity-neutral dopant is carbon. 
     
     
         45 . The integrated circuitry of  claim 34  wherein the conductivity-neutral dopant is germanium.