Sti region for small fin pitch in finfet devices

Abstract

The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. A structure is disclosed. The structure may include: a semiconductor substrate; a plurality of fins on the semiconductor substrate; a plurality of caps on the fins; an isolation layer on the semiconductor substrate and between the plurality of fins, the isolation layer having an upper surface that is substantially flush with an upper surface of the plurality of caps; an isolation trench in the semiconductor substrate; a fin trench where one of the plurality of fins and one of the plurality of caps have been removed; and insulating material in the isolation trench and the fin trench to form an isolation region, the isolation region having an upper surface that is substantially flush with the upper surface of the isolation layer.

What is claimed is: 
     
         1 . A structure, comprising:
 a semiconductor substrate;   a plurality of fins on the semiconductor substrate;   a plurality of caps on the fins;   an isolation layer on the semiconductor substrate and between the plurality of fins, the isolation layer having an upper surface that is substantially flush with an upper surface of the plurality of caps;   an isolation trench in the semiconductor substrate;   a fin trench where one of the plurality of fins and one of the plurality of caps have been removed; and   insulating material in the isolation trench and the fin trench to form an isolation region, the isolation region having an upper surface that is substantially flush with the upper surface of the isolation layer.   
     
     
         2 . The structure of  claim 1 , wherein the isolation trench has an entire width that is approximately equal to an entire width of one of the plurality of fins.