Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Abstract

The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al 2 O 3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

What is claimed is: 
     
         1 . A method for fabricating a device, the method comprising:
 depositing a dielectric etch stop layer directly on a plurality of wordlines disposed in an array portion of a substrate and a plurality of gates disposed in a peripheral portion of the substrate;   removing the dielectric etch stop layer from the peripheral portion of the substrate;   removing a portion, but not the entirety, of the dielectric etch stop layer from the array portion of the substrate;   depositing a dielectric layer over each of the dielectric etch stop layer, the array portion, and the peripheral portion; and   removing a portion, but not the entirety, of the dielectric layer to at least partially expose a conductive element associated with at least one of the plurality of wordlines.   
     
     
         2 . The method, as set forth in  claim 1 , comprising etching a pattern into the dielectric etch stop layer to expose a plurality of regions in the array portion. 
     
     
         3 . The method, as set forth in  claim 1 , comprising depositing a conductive layer over each of the dielectric etch stop layer, the array portion and the peripheral portion to form a local interconnect between the array portion and the peripheral portion. 
     
     
         4 . The method, as set forth in  claim 1 , wherein depositing the dielectric etch stop layer comprises depositing an aluminum oxide (Al 2 O 3 ) material. 
     
     
         5 . The method, as set forth in  claim 1 , comprising:
 forming the plurality of wordlines in the array portion and the plurality of gates in the peripheral portion; and   wherein depositing the dielectric etch stop layer comprises depositing the dielectric etch stop layer over each of the plurality of wordlines and the plurality of gates.   
     
     
         6 . The method, as set forth in  claim 5 , comprising:
 doping a first plurality of active areas adjacent to at least one of the plurality of wordlines in the array portion; and   doping a second plurality of active areas adjacent to at least one of the plurality of gates in the peripheral portion.   
     
     
         7 . The method, as set forth in  claim 1 , is performed in the recited order. 
     
     
         8 . A method for fabricating a device with a dielectric etch stop layer, the method comprising:
 forming a first plurality of structures in an array portion of a substrate and a second plurality of structures in the peripheral portion of the substrate, wherein the second plurality of structures comprises gates;   depositing a dielectric etch stop layer directly on the first plurality of structures and the second plurality of structures;   removing the dielectric etch stop layer from the second plurality of structures;   etching a pattern into the dielectric etch stop layer to expose at least one of the first plurality of structures;   depositing a dielectric layer over the first plurality of structures in the array portion of the substrate and the second plurality of structures in the peripheral portion of the substrate; and   removing a portion, but not the entirety, of the dielectric layer with an etchant to expose at least one of the first plurality of structures and at least one of the second plurality of structures, wherein the etchant is more selective to the dielectric layer than the dielectric etch stop layer.   
     
     
         9 . The method, as set forth in  claim 8 , comprising depositing a conductive layer over each of the dielectric etch stop layer, the dielectric layer, the at least one of the first plurality of structures and at least one of the second plurality of structures. 
     
     
         10 . The method, as set forth in  claim 8 , wherein depositing the dielectric etch stop layer comprises depositing an aluminum oxide (Al 2 O 3 ) material. 
     
     
         11 . The method, as set forth in  claim 8 , is performed in the recited order. 
     
     
         12 . The method, as set forth in  claim 8 , wherein depositing the dielectric layer comprises depositing a tetraethylorthosilicate (TEOS) material. 
     
     
         13 . The method, as set forth in  claim 8 , wherein the first plurality of structures comprise a plurality of wordlines, buried digit lines, bitlines, or a combination thereof. 
     
     
         14 . The method, as set forth in  claim 8 , wherein the second plurality of structures comprise a plurality of doped regions. 
     
     
         15 . The method, as set forth in  claim 8 , comprising depositing a second dielectric layer over each of the dielectric layer, the dielectric etch stop layer, the array portion, and the peripheral portion. 
     
     
         16 . The method, as set forth in  claim 15 , comprising removing a plurality of portions of the second dielectric layer from each of the dielectric layer, the dielectric etch stop layer, the array portion, and the peripheral portion 
     
     
         17 . A method for fabricating a device, the method comprising:
 depositing a dielectric etch stop layer directly on a plurality of wordlines disposed in an array portion of a substrate and a plurality of gates disposed in a peripheral portion of the substrate;   removing at least a portion of the dielectric etch stop layer from the peripheral portion of the substrate;   removing only a portion of the dielectric etch stop layer from the array portion of the substrate;   depositing a dielectric layer over each of the dielectric etch stop layer, the array portion, and the peripheral portion; and   depositing a buried digit line or local interconnect layer over each of the dielectric etch stop layer, the array portion, and the peripheral portion.   
     
     
         18 . The method, as set forth in  claim 17 , is performed in the recited order. 
     
     
         19 . The method, as set forth in  claim 17 , wherein depositing the dielectric etch stop layer comprises depositing an aluminum oxide (Al 2 O 3 ) material. 
     
     
         20 . The method, as set forth in  claim 17 , wherein depositing the dielectric layer comprises depositing a tetraethylorthosilicate (TEOS) material.