Nonvolatile semiconductor memory device

Abstract

According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.

What is claimed is: 
     
         1 . A memory device, comprising:
 a first memory string including a first memory cell and a second memory cell connected in series, the first memory string including a first semiconductor layer extending in a first direction, the first direction being parallel to a substrate;   a second memory string including a third memory cell and a fourth memory cell connected in series, the second memory string including a second semiconductor layer extending in the first direction, and the second memory string being disposed above the first memory string; and   a controller configured to perform a first operation for writing the same data to both the first memory cell and third memory cell, the first operation including a first cycle, and a second cycle, the controller being configured to apply a first voltage difference between the first semiconductor layer and a gate of the first memory cell when writing data to the first memory cell in the first cycle, apply a second voltage difference between the first semiconductor layer and the gate of the first memory cell when writing data to the first memory cell in the second cycle, apply a third voltage difference between the second semiconductor layer and a gate of the third memory cell when writing data to the third memory cell in the first cycle, and apply a fourth voltage difference between the second semiconductor layer and the gate of the third memory cell when writing data to the third memory cell in the second cycle, a value of obtained by subtracting the first voltage difference from the second voltage difference being different from a value of obtained by subtracting the third voltage difference from the fourth voltage difference.   
     
     
         2 . The memory device according to  claim 1 , wherein the second voltage difference is larger than the first voltage difference, and the fourth voltage difference is larger than the third voltage difference. 
     
     
         3 . The memory device according to  claim 1 , further comprising:
 a first word line electrically connected to the first memory cell;   a second word line electrically connected to the second memory cell;   a third word line electrically connected to the third memory cell; and   a fourth word line electrically connected to the fourth memory cell.   
     
     
         4 . The memory device according to  claim 3 , wherein a first voltage is applied to the first word line when writing data to the first memory cell in the first cycle, a second voltage is applied to the first word line when writing data to the first memory cell in the second cycle, a third voltage is applied to the third word line when writing data to the third memory cell in the first cycle, a fourth voltage is applied to the third word line when writing data to the third memory cell in the second cycle, and a voltage difference between the first voltage and the second voltage is different from a voltage difference between the third voltage and the fourth voltage. 
     
     
         5 . The memory device according to  claim 4 , wherein the second voltage difference is larger than the first voltage difference, and the fourth voltage difference is larger than the third voltage difference. 
     
     
         6 . The memory device according to  claim 1 , further comprising:
 a bit line electrically connected to the first memory string and the second memory string.   
     
     
         7 . The memory device according to  claim 1 , further comprising:
 a source line electrically connected to the first memory string and the second memory string.