Vector memory access instructions for big-endian element ordered and little-endian element ordered computer code and data

Abstract

Embodiments relate to vector memory access instructions for big-endian (BE) element ordered computer code and little-endian (LE) element ordered computer code. An aspect includes determining a mode of a computer system comprising one of a BE mode and an LE mode. Another aspect includes determining a code type comprising one of BE code and LE code. Another aspect includes determining a data type of data in a main memory that is associated with the object code comprising one of BE data and LE data. Another aspect includes based on the mode, code type, and data type, inserting a memory access instruction into the object code to perform a memory access associated with the vector in the object code, such that the memory access instruction performs element ordering of elements of the vector, and data ordering within the elements of the vector, in accordance with the determined mode, code type, and data type.

What is claimed is: 
     
         1 . A computer implemented method for vector memory access instructions for big-endian (BE) element ordered computer code and little-endian (LE) element ordered computer code, the method comprising:
 determining, by a computer comprising a main memory and a processor, an element ordering of a vector memory access instruction, the element ordering comprising one of a BE mode and an LE mode;   determining a byte ordering of data in the main memory, wherein the byte ordering of the data comprises one of BE data and LE data; and   determining an element data type of a vector associated with the vector memory access instruction;   based on determining that the element ordering of the vector memory instruction is the BE mode and the byte ordering of the data is BE data, or based on determining that the element ordering of the vector memory instruction is the LE mode and the byte ordering of the data is LE data, transferring vector elements of the vector of the determined element data type in a first manner corresponding to a same order as the byte ordering between the main memory and the processor; and   based on determining that the element ordering of the vector memory instruction is the LE mode and the byte ordering of the data is BE data, or based on determining that the element ordering of the vector memory instruction is the LE mode and the byte ordering of the data is BE data, transferring vector elements of the vector of the determined element data type in a second manner corresponding to an opposite order as the byte ordering between the main memory and the processor.   
     
     
         2 . The method of  claim 1 , wherein transferring the vector elements comprises transferring the vector elements between an arbitrary address in the main memory and at least one register of the processor that is designated by the vector memory access instruction. 
     
     
         3 . The method of  claim 1 , wherein transferring the vector elements corresponds to one of a BE ordering and a LE ordering based on the data ordering being BE data. 
     
     
         4 . The method of  claim 1 , wherein transferring the vector elements corresponds to one of a BE ordering and a LE ordering based on the data ordering being LE data. 
     
     
         5 . The method of  claim 1 , wherein the transferring for a vector comprising a single vector element corresponds to transferring the single vector element in the second manner based on the element ordering being the same as the byte ordering. 
     
     
         6 . The method of  claim 1 , wherein the vector access instruction is part of object code that comprises both BE element ordered object code and LE element ordered object code, and wherein executing the object code comprising executing the BE element ordered object code using a first group of memory access instructions corresponding to the first manner, and executing the LE element ordered object using a second group of memory access instruction that correspond to the second manner. 
     
     
         7 . The method of  claim 1 , wherein the element ordering of the data is determined based on a machine state register (MSR). 
     
     
         8 . The method of  claim 1 , wherein the element ordering of the data is determined based on an encoding of the vector memory access instruction.