Enhanced core power reduction

Abstract

An IC includes a first core and a second core configured to operate in a common power domain. In a case tasks are running on the at least two cores, a control circuit is configured to adjust a voltage for the common power domain based on an electrical characteristic of the first core with a higher threshold operating voltage than the second core, and to adjust an operating frequency for the second core which can run at a higher operating frequency than the first core based on the voltage for the common power domain. In another case, a task or tasks are run on one core only. An IC includes a control circuit configured to select a core with lower minimum operating voltage for the task or tasks based on electrical characteristics of the cores to lower the voltage of the common power domain.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first core and a second core configured to operate in a common power domain; and   a control circuit configured to adjust a voltage for the common power domain based on an electrical characteristic of the first core, which is different from an electrical characteristic of the second core, and to adjust an operating frequency for the second core based on the voltage for the common power domain.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the first core has a higher threshold operating voltage than the second core for a same operating frequency. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the voltage for the common power domain comprises a threshold operating voltage of the first core. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the operating frequency for the second core comprises an upper threshold frequency of the second core supported by the voltage for the common power domain. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the control circuit is further configured to adjust an operating frequency for the first core based on the voltage for the common power domain, wherein the operating frequency for the first core comprises an upper threshold frequency of the first core supported by the voltage for the common power domain. 
     
     
         6 . The integrated circuit of  claim 1 , further comprising:
 N cores in the common power domain, including the first core and the second core; and   a plurality of sensor circuits configured to output electrical characteristics indicating threshold operating voltages of N core,   wherein the control circuit is configured to select cores for tasks based on an ascending order of the threshold operating voltages of the N cores, and wherein a core having a lower threshold operating voltage is selected before a core having a higher threshold operating voltage.   
     
     
         7 . The integrated circuit of  claim 1 , wherein the electrical characteristic comprises a speed performance associated with each core. 
     
     
         8 . The integrated circuit of  claim 1 , further comprising sensor circuits configured to output information corresponding to the electrical characteristic of each core, wherein the control circuit is configured to adjust the voltage for the common power domain and adjust the operating frequency for the second core based on the information output by the sensor circuits. 
     
     
         9 . The integrated circuit of  claim 8 , wherein the sensor circuits comprises a ring oscillator or a delay line circuit. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the control circuit is further configured to allocate task workload to a core among the first core and the second core having a lower threshold operating voltage or a higher operating frequency supported by the voltage for the common power domain. 
     
     
         11 . An integrated circuit, comprising:
 a first core and a second core configured to operate in a common power domain; and   a control circuit configured to select the first core or the second core for a task based on an electrical characteristic of the first core and an electrical characteristic of the second core, wherein the selected first core or second core enters into a low power mode or power collapse mode in response to completion of the task.   
     
     
         12 . The integrated circuit of  claim 11 , further comprising
 a first sensor circuit configured to output information corresponding to the electrical characteristic of the first core; and   a second sensor circuit configured to output information corresponding to the electrical characteristic of the second core,   wherein the control circuit is configured to select the first core or the second core for the task based on the information output by the first sensor circuit and the information output by the second sensor circuit.   
     
     
         13 . The integrated circuit of  claim 12 , wherein the electrical characteristic of the first core or the electrical characteristic of the second core comprises a speed performance. 
     
     
         14 . The integrated circuit of  claim 12 , wherein the control circuit is further configured to adjust a voltage for the common power domain based on the output information of the first sensor circuit and the output information of the second sensor circuit. 
     
     
         15 . The integrated circuit of  claim 12 , wherein the control circuit is further configured to determine an operating frequency for the first core or the second core selected for the task. 
     
     
         16 . A method for operating an integrated circuit, comprising:
 operating a first core and a second core in a common power domain; and   adjusting a voltage for the common power domain based on an electrical characteristic of the first core, which is different from an electrical characteristic of the second core; and   adjusting an operating frequency for the second core based on the voltage for the common power domain.   
     
     
         17 . The method of  claim 16 , wherein the first core has a higher threshold operating voltage than the second core for a same operating frequency. 
     
     
         18 . The method of  claim 16 , wherein the voltage for the common power domain comprises a threshold operating voltage of the first core. 
     
     
         19 . The method of  claim 18 , wherein the operating frequency for the second core comprises an upper threshold frequency of the second core supported by the voltage for the common power domain. 
     
     
         20 . The method of  claim 19 , further comprising adjusting an operating frequency for the first core based on the voltage for the common power domain, wherein the operating frequency for the first core comprises an upper threshold frequency of the first core supported by the voltage for the common power domain. 
     
     
         21 . The method of  claim 16 , further comprising entering by the second core into a low power mode or power collapse mode in response to completion a task. 
     
     
         22 . The method of  claim 16 , wherein the electrical characteristic comprises a speed performance associated with the first core. 
     
     
         23 . The method of  claim 16 , further comprising outputting, by sensor circuits, information corresponding to the electrical characteristic of each core, wherein the adjusting the voltage for the common power domain and the adjusting the operating frequency for the second core are based on the information output by the sensor circuits. 
     
     
         24 . The method of  claim 23 , wherein the sensor circuits comprises a ring oscillator or a delay line circuit. 
     
     
         25 . The method of  claim 16 , further comprising allocating task workload to a core among the first core and the second core having a lower threshold operating voltage or a higher operating frequency supported by the voltage for the common power domain. 
     
     
         26 . A method for operating an integrated circuit, comprising:
 operating a first core and a second core in a common power domain;   selecting the first core or the second core for a task based on an electrical characteristic of the first core and an electrical characteristic of the second core;   entering by the selected first core or second core into a low power mode or power collapse mode in response to completion of the task.   
     
     
         27 . The method of  claim 26 , further comprising
 outputting, by a first sensor circuit, information corresponding to the electrical characteristic of the first core; and   outputting, by a second sensor circuit, information corresponding to the electrical characteristic of the second core,   wherein the selecting the first core or the second core for the task is based on the information output by the first sensor circuit and the information output by the second sensor circuit.   
     
     
         28 . The method of  claim 27 , wherein the electrical characteristic of the first core or the electrical characteristic of the second core comprises a speed performance. 
     
     
         29 . The method of  claim 27 , further comprising adjusting a voltage for the common power domain based on the output information of the first sensor circuit and the output information of the second sensor circuit. 
     
     
         30 . The method of  claim 27 , further comprising adjusting an operating frequency for the first core or the second core selected for the task.