Power measurement device

Abstract

A power measurement device for sampling current or voltage signals of a power system to produce a 1-bit delta-sigma bitstream. The power measurement device includes a frequency locked loop for determining the power system frequency directly from the 1-bit delta-sigma bitstream. The frequency locked loop includes a 1-bit rotate CORDIC that is configured to produce difference signals having a multi-bit word for each bit of the 1-bit delta-sigma bitstream, and a phase error calculator that determines the difference between the phase of the power system frequency and a phase ramp generated from a frequency measurement value in a frequency register. The phase error calculator feeds back a phase correction signal to the frequency register to lock the frequency measurement value to the power system frequency.

What is claimed is: 
     
         1 . A method of measuring power system characteristics, the power system having a system frequency and one or more phases, the method comprising:
 sampling one of voltage or current of the power system to produce a 1-bit delta-sigma modulated bitstream;   generating in-phase and quadrature difference signals from the 1-bit delta-sigma bitstream using a 1-bit rotate CORDIC receiving a phase ramp signal, the difference signals each having a multi-bit word for each bit of the 1-bit delta-sigma signal, wherein the phase ramp signal has a periodicity based upon a frequency value; and   generating a phase error signal based upon a difference between the difference signals, wherein the difference indicates an error between a phase of the phase ramp signal and the phase of the system frequency contained within the 1-bit delta-sigma signal; and   adjusting the frequency value to lock it to the system frequency based upon the phase error signal.   
     
     
         2 . The method claimed in  claim 1 , wherein the 1-bit rotate CORDIC receives the 1-bit delta-sigma signal from a delta-sigma modulator without any low-pass filtering. 
     
     
         3 . The method claimed in  claim 1 , further including low pass filtering outputs of the 1-bit rotate CORDIC to produce the difference signals. 
     
     
         4 . The method claimed in  claim 1 , further including sampling one of voltage and current on one or more phases of the power system thereby producing one or more additional 1-bit delta-sigma signals, and further comprising generating in-phase and quadrature difference signals for each of the one or more additional 1-bit delta-sigma bitstream using respective one or more 1-bit rotate CORDICs and producing respective additional in-phase and quadrature difference signals. 
     
     
         5 . The method claimed in  claim 1 , wherein generating the phase error signal comprises using a vector CORDIC. 
     
     
         6 . The method claimed in  claim 1 , further comprising transmitting the frequency value to a remote location together with a time stamp. 
     
     
         7 . The method claimed in  claim 1 , further comprising determining a RMS value for the voltage or current based upon the 1-bit delta-sigma signal. 
     
     
         8 . A power measurement device for measuring phase and frequency in multi-phase power system, the power system having a system frequency, the device comprising:
 a plurality of delta-sigma modulators each measuring one of voltage or current on one of the phases in the multi-phase power system and outputting a 1-bit delta-sigma signal;   a phase accumulator configured to produce a phase ramp signal having a periodicity determined by a frequency value;   a 1-bit rotate CORDIC for each delta-sigma modulator, wherein each 1-bit rotate CORDIC receives the phase ramp signal and a respective one of the 1-bit delta-sigma signals and outputs an in-phase difference signal and a quadrature-phase difference signal, the difference signals each having a multi-bit word for each bit of the 1-bit delta-sigma signal; and   a phase error calculator for each 1-bit rotate CORDIC to receive the difference signals from that 1-bit rotate CORDIC and to output a phase error signal based upon the difference between a phase of the phase ramp signal and the phase of the respective one of the 1-bit delta-sigma signals,   wherein one of the phase error calculators corrects the frequency value using its phase error signal to lock it to the system frequency, and wherein the other of the phase error calculators corrects a respective phase offset value measured for its respective one of the 1-bit delta-sigma signals using its respective phase error signal.   
     
     
         9 . The power measurement device claimed in  claim 8 , wherein the same phase ramp signal is received by each of the 1-bit rotate CORDICs. 
     
     
         10 . The power measurement device claimed in  claim 8 , wherein the phase error calculators comprise vector CORDICs. 
     
     
         11 . The power measurement device claimed in  claim 8 , wherein the 1-bit rotate CORDICs comprise m stage CORDICs and the multi-bit word is 2m±1 bits for every input bit of the 1-bit delta-sigma signal. 
     
     
         12 . The power measurement device claimed in  claim 8 , further comprising a register to store the frequency value and respective registers to store the phase offset values. 
     
     
         13 . The power measurement device claimed in  claim 8 , wherein the phase accumulator receives an input based upon its output, the frequency value and a time correction signal. 
     
     
         14 . The power measurement device claimed in  claim 13 , wherein the input comprises the phase accumulator output plus a step size based on the frequency value adjusted by the time correction signal, clocked based on a local oscillator, and wherein the time correction signal corrects for error in the local oscillator. 
     
     
         15 . A method of measuring phase and frequency in multi-phase power system, the power system having a system frequency, the method comprising:
 measuring one of voltage or current on each one of the phases in the multi-phase power system and delta-sigma modulating each of the measurements to output 1-bit delta-sigma signals;   generating a phase ramp signal using a phase accumulator, the phase ramp signal having a periodicity determined by a frequency value;   for each of the 1-bit delta-sigma signals, producing an in-phase difference signal and a quadrature-phase difference signal using a respective 1-bit rotate CORDIC, wherein each 1-bit rotate CORDIC receives the phase ramp signal and its respective one of the 1-bit delta-sigma signals, the difference signals each having a multi-bit word for each bit of the 1-bit delta-sigma signal;   for each pair of difference signals, generating a phase error signal based upon the difference between a phase of the phase ramp signal and the phase of the respective one of the 1-bit delta-sigma signals;   correcting the frequency value to lock it to the system frequency using one of the phase error signals; and   for each of the other phase error signals, correcting a respective phase offset value measured for its respective one of the 1-bit delta-sigma signals.   
     
     
         16 . The method claimed in  claim 15 , wherein the same phase ramp signal is received by each of the 1-bit rotate CORDICs. 
     
     
         17 . The method claimed in  claim 15 , wherein the 1-bit rotate CORDICs comprise m stage CORDICs and wherein producing the in-phase difference signal or the quadrature-phase difference signal comprises producing a multi-bit word of 2m±1 bits for every input bit of the 1-bit delta-sigma signal. 
     
     
         18 . The method claimed in  claim 15 , further comprising storing the frequency value in a register and storing the phase offset values in respective registers. 
     
     
         19 . The method claimed in  claim 15 , wherein generating the phase ramp signal comprises receiving an input based upon a feedback phase ramp signal, the frequency value and a time correction signal. 
     
     
         20 . The method claimed in  claim 19 , wherein the input comprises the phase accumulator output plus a step size based on the frequency value adjusted by the time correction signal, clocked based on a local oscillator, and wherein the time correction signal corrects for error in the local oscillator.