Semiconductor devices with a layer of material having a plurality of source/drain trenches

Abstract

One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

What is claimed: 
     
         1 . A device, comprising:
 an active region defined in a semiconductor substrate;   a layer of material positioned above said semiconductor substrate;   first and second laterally spaced-apart source/drain trenches defined in said layer of material above said active region;   first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively;   a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches in said layer of material, wherein portions of said layer of material remains positioned between said first and second laterally spaced-apart source/drain trenches and said gate trench;   a gate structure positioned within said gate trench; and   a gate cap layer positioned above said gate structure.   
     
     
         2 . The device of  claim 1 , wherein said device is a FinFET device and wherein said first and second laterally spaced-apart source/drain regions are each comprised of at least one fin. 
     
     
         3 . The device of  claim 1 , wherein said device is a planar device and wherein said first and second laterally spaced-apart source/drain regions are each comprised of a substantially uniform layer of semiconductor material having a substantially uniform and planar upper surface. 
     
     
         4 . The device of  claim 1 , wherein said gate structure is comprised of a high-k gate insulation material layer and a layer of conductive material positioned above said high-k gate insulation material layer. 
     
     
         5 . The device of  claim 1 , wherein said layer of material is a material having a dielectric constant equal to or less than 7. 
     
     
         6 . The device of  claim 1 , wherein said gate structure abuts and engages sidewalls of said gate trench. 
     
     
         7 . The device of  claim 1 , wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench. 
     
     
         8 . The device of  claim 1 , wherein said gate trench is formed entirely within said layer of material. 
     
     
         9 . The device of  claim 1 , wherein said layer of material is comprised of one of silicon-carbon-boron-nitride (SiB x C y N) or silicon nitride (SiN). 
     
     
         10 . The device of  claim 1 , wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively. 
     
     
         11 . The device of  claim 1 , further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate. 
     
     
         12 . A device, comprising:
 an active region defined in a semiconductor substrate;   a layer of material positioned above said semiconductor substrate, said layer of material having a dielectric constant equal to or less than 7;   first and second laterally spaced-apart source/drain trenches defined in said layer of material above said active region;   first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively, wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench;   a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches in said layer of material, wherein portions of said layer of material remain positioned between said first and second laterally spaced-apart source/drain trenches and said gate trench;   a gate structure positioned within said gate trench, wherein said gate structure abuts and engages sidewalls of said gate trench; and   a gate cap layer positioned above said gate structure.   
     
     
         13 . The device of  claim 12 , wherein said gate trench is formed entirely within said layer of material and wherein said gate structure abuts and engages all sidewalls of said gate trench. 
     
     
         14 . The device of  claim 12 , wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively. 
     
     
         15 . The device of  claim 12 , further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate. 
     
     
         16 . A device, comprising:
 an active region defined in a semiconductor substrate, a layer of material positioned above said semiconductor substrate;   first and second laterally spaced-apart source/drain trenches formed in said layer of material above said active region;   first and second conductive source/drain contact structures positioned within said first and second laterally spaced-apart source/drain trenches, respectively;   a gate trench formed at least partially in said layer of material between said first and second laterally spaced-apart source/drain trenches, wherein first portions of said layer of material remain positioned between said first and second source/drain trenches and said gate trench above said active region and second portions of said layer of material remain positioned between said first and second source/drain trenches and said gate trench outside of said active region, wherein said second portions of said layer of material are thicker in a gate length direction of said device than are said first portions of said layer of material; and   a gate structure positioned within said gate trench, wherein a first portion of sidewalls of said gate structure are positioned adjacent said first portions of said layer of material and a second portion of said sidewalls of said gate structure are positioned adjacent said second portions of said layer of material.   
     
     
         17 . The device of  claim 16 , wherein said layer of material is a material having a dielectric constant equal to or less than 7. 
     
     
         18 . The device of  claim 16 , wherein said gate structure abuts and engages said first and second portions of said layer of material. 
     
     
         19 . The device of  claim 16 , wherein said first conductive source/drain contact structure abuts and engages sidewalls of said first source/drain trench and said second conductive source/drain contact structure abuts and engages sidewalls of said second source/drain trench. 
     
     
         20 . The device of  claim 16 , wherein said gate trench is formed entirely within said layer of material. 
     
     
         21 . The device of  claim 16 , wherein each of said first and second conductive source/drain contact structures have first and second upper surfaces, respectively, wherein said first and second upper surfaces are each positioned level with or below an upper surface of said first and second laterally spaced-apart source/drain trenches, respectively. 
     
     
         22 . The device of  claim 16 , further comprising first and second semiconductor material regions positioned within said first and second laterally spaced-apart source/drain trenches, respectively, and below said first and second conductive source/drain contact structures, respectively, at least a portion of said first and second semiconductor material regions being positioned at a level that is above a level of an upper surface of said semiconductor substrate.