Low energy ion implantation of a junction butting region

Abstract

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

1 . An embedded dynamic random access memory (eDRAM) structure comprising:
 a first gate stack and a second gate stack on a semiconductor on insulator (SOI) layer;   a source-drain (S-D) region between the first gate stack and the second gate stack, wherein the S-D region extends from an upper surface of the SOI layer to an interior region of the SOI layer, and wherein the S-D region has a bottom and a pair of sidewalls;   a silicide layer on the S-D region;   a protective layer on the SOI layer, the first gate stack, the second gate stack; and   a low energy junction butting region directly below the S-D region, the low energy junction butting region extending from the bottom of the S-D region to an isolation layer immediately below the SOI layer.   
     
     
         2 . The eDRAM structure of  claim 1 , further comprising:
 a dielectric layer on the protective layer and the silicide layer; and   a contact extending from an upper surface of the dielectric layer to an upper surface of the silicide layer.   
     
     
         3 . The eDRAM structure of  claim 1 , the junction butting region having a rounded bottom surface. 
     
     
         4 . The eDRAM structure of  claim 1 , the protective layer comprising a nitride. 
     
     
         5 . The eDRAM structure of  claim 1 , the junction butting region and the S-D region comprising a N-type dopant and the SOI layer comprising a P-type dopant. 
     
     
         6 . The eDRAM structure of  claim 1 , the junction butting region and the S-D region comprising a P-type dopant and the SOI layer comprising a N-type dopant. 
     
     
         7 . The eDRAM structure of  claim 1 , further comprising an upper portion of the junction butting region adjacent to and contacting the pair of sidewalls. 
     
     
         8 . The eDRAM structure of  claim 1 , the junction butting region having a graded dopant profile such that a concentration of a dopant is higher in a first portion of the junction butting region adjacent to the S-D region and lower in a second portion of the junction butting region adjacent to the isolation layer. 
     
     
         9 . A memory structure comprising:
 a first gate stack and a second gate stack on a semiconductor on insulator (SOI) layer in an active wordline region;   a source-drain (S-D) region in the SOI layer between the first gate stack and the second gate stack, the S-D region extending from an upper surface of the SOI layer to an interior region of the SOI layer and having a bottom surface; and,   a junction butting region in an active word line region directly below the bottom surface of the S-D region, the junction butting region extending from the bottom surface of the S-D region to an isolation layer immediately below the SOI layer and having a width that is less than or equal to a horizontal distance between the first gate stack and the second gate stack.   
     
     
         10 . The memory structure of  claim 9 , further comprising:
 a protective layer on the first gate stack and the second gate stack;   a silicide layer on a top surface of the SOI layer positioned laterally between the first gate stack and the second gate stack and separated from the first gate stack and the second gate stack by the protective layer, the silicide layer being aligned above the S-D region;   a dielectric layer on the protective layer and the silicide layer; and   a contact extending from an upper surface of the dielectric layer to an upper surface of the silicide layer.   
     
     
         11 . The memory structure of  claim 10 , the protective layer comprising a nitride layer. 
     
     
         12 . The memory structure of  claim 9 , the S-D region and the junction butting region having rounded bottom surfaces. 
     
     
         13 . The memory structure of  claim 9 , the junction butting region and the S-D region being doped with a N-type dopant and the SOI layer being doped with a P-type dopant. 
     
     
         14 . The memory structure of  claim 9 , the junction butting region and the S-D region being doped with a P-type dopant and the SOI layer being doped with an N-type dopant. 
     
     
         15 . The memory structure of  claim 9 , the S-D region further having vertical sidewalls and the junction butting region further having an upper adjacent to and contacting the vertical sidewalls. 
     
     
         16 . The memory structure of  claim 9 , the junction butting region having a graded dopant profile such that a concentration of a dopant is higher in a first portion of the junction butting region adjacent to the S-D region and lower in a second portion of the junction butting region adjacent to the isolation layer. 
     
     
         17 . A memory structure comprising:
 a first gate stack and a second gate stack on a semiconductor on insulator (SOI) layer;   a source-drain (S-D) region in the SOI layer between the first gate stack and the second gate stack, the S-D region comprising:
 a trench extending from an upper surface of the SOI layer to an interior region of the SOI layer, the trench having a bottom surface and sidewalls; and, 
 an epitaxial semiconductor layer having a specific type conductivity filling the trench; and, 
   a junction butting region in the SOI layer directly adjacent to the bottom surface and the sidewalls,   the junction butting region comprising a dopant implant region having the specific type conductivity, and   the junction butting region extending vertically from the bottom surface to an isolation layer immediately below the SOI layer and having a width that is less than a horizontal distance between the first gate stack and the second gate stack.   
     
     
         18 . The memory structure of  claim 17 , further comprising:
 a protective layer on the first gate stack and the second gate stack;   a silicide layer on a top surface of the SOI layer positioned laterally between the first gate stack and the second gate stack and separated from the first gate stack and the second gate stack by the protective layer, the silicide layer being aligned above the S-D region;   a dielectric layer on the protective layer and the silicide layer; and   a contact extending from an upper surface of the dielectric layer to an upper surface of the silicide layer.   
     
     
         19 . The memory structure of  claim 17 , the S-D region and the junction butting region having a rounded bottom surfaces. 
     
     
         20 . The memory structure of  claim 17 , the junction butting region having a graded dopant profile such that a concentration of a dopant having the specific type conductivity is higher in a first portion of the junction butting region adjacent to the S-D region and lower in a second portion of the junction butting region adjacent to the isolation layer.