Gate structures for cmos based integrated circuit products

Abstract

An integrated circuit product includes an NMOS transistor having a gate structure comprised of an NMOS gate insulation layer comprised of a high-k gate insulation material, an NMOS metal silicide region positioned above the NMOS gate insulation layer, and an NMOS metal layer positioned on the NMOS metal silicide region, and a PMOS transistor having a gate structure comprised of a PMOS gate insulation layer comprised of the high-k gate insulation material, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide region positioned above the first PMOS metal layer, wherein the PMOS metal silicide region and the NMOS metal silicide region are comprised of the same metal silicide, and a second PMOS metal layer positioned on the PMOS metal silicide region, wherein the NMOS metal layer and second PMOS metal layer are comprised of the same material.

What is claimed: 
     
         1 . An integrated circuit product, comprising:
 an NMOS transistor having a gate structure comprised of:
 an NMOS gate insulation layer comprised of a high-k gate insulation material; 
 an NMOS metal silicide region positioned above said NMOS gate insulation layer, wherein said NMOS metal silicide region has a generally rectangular cross-sectional configuration; and 
 an NMOS metal layer positioned on said NMOS metal silicide region; and 
   a PMOS transistor having a gate structure comprised of:
 a PMOS gate insulation layer comprised of said high-k gate insulation material; 
 a first PMOS metal layer positioned on said PMOS gate insulation layer; 
 a PMOS metal silicide region positioned above said first PMOS metal layer, wherein said PMOS metal silicide region has a generally T-shaped cross-sectional configuration and wherein said PMOS metal silicide region and said NMOS metal silicide region are comprised of the same metal silicide; and 
 a second PMOS metal layer positioned on said PMOS metal silicide region, wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same material. 
   
     
     
         2 . The device of  claim 1 , wherein said NMOS metal silicide region is positioned on said NMOS gate insulation layer. 
     
     
         3 . The device of  claim 1 , wherein said PMOS metal silicide region is positioned on said first PMOS metal layer. 
     
     
         4 . The device of  claim 2 , wherein said first PMOS metal layer is titanium nitride. 
     
     
         5 . The device of  claim 2 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of tungsten. 
     
     
         6 . The device of  claim 5 , wherein said NMOS metal silicide region and said PMOS metal silicide region are comprised of tungsten silicide. 
     
     
         7 . The device of  claim 2 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same refractory metal. 
     
     
         8 . The device of  claim 2 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same transition metal. 
     
     
         9 . The device of  claim 2 , further comprising:
 an NMOS gate cap layer that is positioned on and in contact with said NMOS metal layer; and   a PMOS gate cap layer that is positioned on and in contact with said second PMOS metal, wherein said NMOS cap layer and said PMOS cap layer are comprised of the same material.   
     
     
         10 . An integrated circuit product, comprising:
 an NMOS transistor having a gate structure comprised of:
 an NMOS gate insulation layer comprised of a high-k gate insulation material; 
 an NMOS metal silicide region positioned on and in contact with said NMOS gate insulation layer, wherein said NMOS metal silicide region has a generally rectangular cross-sectional configuration; and 
 an NMOS metal layer positioned on said NMOS metal silicide region; and 
   a PMOS transistor having a gate structure comprised of:
 a PMOS gate insulation layer comprised of said high-k gate insulation material; 
 a first PMOS metal layer positioned on and in contact with said PMOS gate insulation layer; 
 a PMOS metal silicide region positioned on and in contact with said first PMOS metal layer, wherein said PMOS metal silicide region has a generally T-shaped cross-sectional configuration and wherein said PMOS metal silicide region and said NMOS metal silicide region are comprised of the same metal silicide; and 
 a second PMOS metal layer positioned on and in contact with said PMOS metal silicide region, wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same material. 
   
     
     
         11 . The device of  claim 10 , wherein said first PMOS metal layer has a U-shaped configuration when viewed in a cross-section taken through said gate structure for said PMOS device in a direction parallel to a gate length direction of said PMOS device. 
     
     
         12 . The device of  claim 11 , wherein a lower portion of said PMOS metal silicide region is positioned within an interior of said U-shaped first PMOS metal layer and an upper portion of said PMOS metal silicide region is positioned outside of said interior of said U-shaped first PMOS metal layer and vertically above a portion of said U-shaped first PMOS metal layer. 
     
     
         13 . The device of  claim 12 , wherein said first PMOS metal layer is titanium nitride. 
     
     
         14 . The device of  claim 10 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of tungsten. 
     
     
         15 . The device of  claim 14 , wherein said NMOS metal silicide region and said PMOS metal silicide region are comprised of tungsten silicide. 
     
     
         16 . The device of  claim 10 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same refractory metal. 
     
     
         17 . The device of  claim 16 , wherein said NMOS metal layer and said second PMOS metal layer are comprised of the same transition metal. 
     
     
         18 . The device of  claim 17 , further comprising:
 an NMOS gate cap layer that is positioned on and in contact with said NMOS metal layer; and   a PMOS gate cap layer that is positioned on and in contact with said second PMOS metal, wherein said NMOS cap layer and said PMOS cap layer are comprised of the same material.   
     
     
         19 . An integrated circuit product, comprising:
 an NMOS transistor having a gate structure comprised of:
 an NMOS gate insulation layer comprised of a high-k gate insulation material; 
 an NMOS metal silicide region positioned on and in contact with said NMOS gate insulation layer, wherein said NMOS metal silicide region has a generally rectangular cross-sectional configuration; and 
 an NMOS metal layer positioned on and in contact with said NMOS metal silicide region; and 
   a PMOS transistor having a gate structure comprised of:
 a PMOS gate insulation layer comprised of said high-k gate insulation material; 
 a first PMOS metal layer comprised of titanium nitride positioned on and in contact with said PMOS gate insulation layer; 
 a PMOS metal silicide region positioned on and in contact with said first PMOS metal layer, wherein said PMOS metal silicide region has a generally T-shaped cross-sectional configuration and wherein said PMOS metal silicide region and said NMOS metal silicide region are comprised of tungsten silicide; and 
 a second PMOS metal layer positioned on and in contact with said PMOS metal silicide region, wherein said NMOS metal layer and said second PMOS metal layer are comprised of tungsten. 
   
     
     
         20 . The device of  claim 19 , wherein said first PMOS metal layer has a U-shaped configuration when viewed in a cross-section taken through said gate structure for said PMOS device in a direction parallel to a gate length direction of said PMOS device. 
     
     
         21 . The device of  claim 20 , wherein a lower portion of said PMOS metal silicide region is positioned within an interior of said U-shaped first PMOS metal layer and an upper portion of said PMOS metal silicide region is positioned outside of said interior of said U-shaped first PMOS metal layer and vertically above a portion of said U-shaped first PMOS metal layer. 
     
     
         22 . The device of  claim 19 , further comprising:
 an NMOS gate cap layer that is positioned on and in contact with said NMOS metal layer; and   a PMOS gate cap layer that is positioned on and in contact with said second PMOS metal, wherein said NMOS cap layer and said PMOS cap layer are comprised of the same material.