Multiple access test architecture for memory storage devices

Abstract

A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral. Thirdly, a second processing unit which on one side is connected to the central processing system and on the other side is connected to the memory storage device via the multiplexer thus providing the second processing unit direct access to the memory storage device. And finally, the multiplexer that can connect either the electronic memory bridge or the second processing system to the memory storage device.

What is claimed is:  
     
         1 . A system architecture for accessing a memory storage device comprising:
 a first central processing system;   an electronic bridge connected on one side to the first central processing system via a standard I/O channel and on the other side to the memory storage device through a multiplexer with the electronic bridge presenting the memory device to the first central processing system as a standard memory peripheral; and   a second processing unit which on one side is connected to the first central processing system and on the other side is connected to the memory storage device via the multiplexer thus providing the second processing unit direct access to the memory storage device; wherein the multiplexer alternatively connects the electronic memory bridge or the second processing system to the memory storage device.   
     
     
         2 . The system architecture of  claim 1  where the I/O channel between the bridge and the central processing system is a USB channel. 
     
     
         3 . The system architecture of  claim 1  where the I/O channel between the bridge and the central processing system is a PCI channel. 
     
     
         4 . The system architecture of  claim 1  where the I/O channel between the bridge and the central processing system is a PCIE channel. 
     
     
         5 . The system architecture of  claim 1  where the memory storage device is an SD card. 
     
     
         6 . The system architecture of  claim 1  where the memory storage device is a compact Flash card. 
     
     
         7 . The system architecture of  claim 1  where the memory storage device is an MMC card. 
     
     
         8 . The system architecture of  claim 1  where the memory storage device is an MS card. 
     
     
         9 . The system architecture of  claim 1  where the memory storage device is a Mini-SD card. 
     
     
         10 . The system architecture of  claim 1  where the memory storage device is a micro SD card. 
     
     
         11 . The system architecture of  claim 1  where in the single bridge connection is replaced by a plurality of bridge circuits, the single multiplexer is replaced by a plurality of multiplexers and the single memory storage device is replaced by a plurality of memory storage devices. 
     
     
         12 . The system architecture of  claim 1  where multiplexer connected to the storage memory device may have a plurality of inputs including the connection to the second processing system, the bridge circuit, and any additional inputs needed to fully power sequence or test the memory storage device as desired by the main computer system. 
     
     
         13 . The system architecture of  claim 1  wherein the second processing system and the multiplexer(s) connected to the memory storage device(s) are on a removable module. 
     
     
         14 . The system architecture of  claim 11  wherein the second processing system and the multiplexer(s) connected to the memory storage device(s) are on a removable module. 
     
     
         15 . The system architecture of  claim 12  wherein the second processing system and the multiplexer(s) connected to the memory storage device(s) are on a removable module. 
     
     
         16 . The system architecture of  claim 13  with modules each one specifically made to support different types of memory storage devices thus creating a universal tester/duplicator for memory storage devices.