Adaptive equalizer

Abstract

An adaptive equalizer ( 100 ) has a signal converter ( 200 ) for performing a fast Fourier transform and/or an inverse fast Fourier transform. The signal converter ( 200 ) has: a first wide-bit memory ( 201 ) capable of reading/writing a plurality of sample signals; a first register group ( 202 ) comprising a plurality of registers capable of accessing the first wide-bit memory ( 201 ); a butterfly computation unit group ( 204 ) comprising a plurality of butterfly computation units; and a first connection switching unit ( 203 ) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.

1 . A signal converter that performs at least one of a fast Fourier transform and an inverse fast Fourier transform, comprising:
 a memory, having a single port, capable of reading and writing signals for 2M samples by two accesses, where M is a natural number;   2M registers accessible to the memory;   M butterfly operation sections; and   a switching control section that switches a connection state between the 2M registers and the M butterfly operation sections.   
     
     
         2 . A signal converter that performs at least one of a fast Fourier transform and an inverse fast Fourier transform, comprising:
 a memory capable of reading and writing signals for 2M samples, where M is a natural number;   2M registers accessible to the memory;   M butterfly operation sections: and   a switching control section that switches a connection state between the 2M registers and the M butterfly operation sections, wherein:   the signal converter includes two pairs of the memory and the 2M registers; and the switching control section switches a connection state (i) between the 2M registers in one of the two pairs and the M butterfly operation sections and (ii) between the 2M registers in the other of the two pairs and the M butterfly operation sections, such that a role of the memory is switched between a memory for output and a memory for input for each stage of the fast Fourier transform and the inverse fast Fourier transform.   
     
     
         3 . The signal converter according to  claim 1 , further comprising:
 a twiddle-factor memory that stores twiddle factors in each stage of the fast Fourier transform and the inverse fast Fourier transform, and that is capable of reading signals for M samples; and   M twiddle-factor registers that are accessible to the twiddle-factor memory, and that obtains the twiddle factors and passes the twiddle factors to the M butterfly operation sections.   
     
     
         4 . The signal converter according to  claim 1 , wherein:
 the memory stores data for M samples collectively in one address.   
     
     
         5 . The signal converter according to  claim 4 , wherein:
 an address space of the memory is 1024/2M, and the signal converter performs the fast Fourier transform/the inverse fast Fourier transform operation at 1024 points.   
     
     
         6 . A signal converter that performs at least one of a fast Fourier transform and an inverse fast Fourier transform, comprising:
 a memory, having two-bank configuration and each bank having a single port, capable of reading and writing signals for 2M samples by one access, where M is a natural number;   2M registers accessible to the memory;   M butterfly operation sections; and   a switching control section that switches a connection state between the 2M registers and the M butterfly operation sections.