Spacer chamfering for a replacement metal gate device

Abstract

Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

What is claimed is: 
     
         1 .- 14 . (canceled) 
     
     
         15 . A semiconductor device, comprising:
 a set of fins formed from a substrate;   a silicon-based layer conformally deposited over the set of fins;   an etch-stop layer formed over the silicon-based layer, the etch-stop layer having a selectivity to at least one of: silicon, oxide, and nitride;   a set of replacement metal gate (RMG) structures formed over the substrate; and   a set of spacers formed along each of the set of RMG structures, wherein a portion of material from each of the set of spacers is removed selective to the etch-stop layer.   
     
     
         16 . The semiconductor device of  claim 15 , further comprising a plurality of epitaxial (epi) junction areas formed along the set of fins between each of the set of RMG structures. 
     
     
         17 . The device according to  claim 15 , the etch-stop layer comprising titanium nitride. 
     
     
         18 . The device according to  claim 15 , wherein the portion of material removed from each of the set of spacers comprises a substantially vertical layer of silicon nitride. 
     
     
         19 . The device according to  claim 18 , wherein the substantially vertical layer is removed using a reactive ion etch. 
     
     
         20 . The device according to  claim 15 , further comprising a source trench isolation oxide formed between each of the set of fins. 
     
     
         21 . The device of  claim 15 , wherein the silicon-based layer comprises silicon oxide (SiO2). 
     
     
         22 . The device of  claim 15 , wherein the set of RMG structures comprises polysilicon, silicon-germanium, Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, or CoSi. 
     
     
         23 . A semiconductor device, comprising:
 a set of fins formed from a substrate;   a source trench isolation (STI) oxide disposed between the fins of the set of fins;   a plurality of epitaxial junction areas disposed on the STI oxide;   an oxide material disposed over each of the plurality of epitaxial junction areas, wherein each oxide material region and its underlying epitaxial junction area together have a first side and second side;   a plurality of first spacers each disposed on the first side of each oxide material region and its underlying epitaxial junction area; and   a plurality of second spacers each disposed on the second side of each oxide material region and its underlying epitaxial junction area;   wherein each of the first spacer and the second spacer have (i) a lower region with a height less than the height of the epitaxial junction area and with a first thickness and (ii) an upper region above the lower region with a second thickness, wherein the second thickness is less than the first thickness.   
     
     
         24 . The semiconductor device of  claim 23 , wherein the substrate comprises silicon, SiGe, or SOI. 
     
     
         25 . The semiconductor device of  claim 23 , wherein the first spacers and the second spacers comprise SiN. 
     
     
         26 . A semiconductor device, comprising:
 a set of fins formed from a substrate;   a silicon-based layer conformally deposited over the set of fins;   an etch-stop layer formed over the silicon-based layer, the etch-stop layer having a selectivity to at least one of: silicon, oxide, and nitride;   a set of replacement metal gate (RMG) structures formed over the substrate; and   a set of spacers formed along each of the set of RMG structures, wherein a portion of material from each of the set of spacers is removed selective to the etch-stop layer, and wherein a plurality of epitaxial (epi) junction areas formed along the set of fins between each of the set of RMG structures.   
     
     
         27 . The semiconductor device of  claim 26 , wherein the etch-stop layer comprising titanium nitride. 
     
     
         28 . The semiconductor device of  claim 26 , wherein the portion of material removed from each of the set of spacers comprises a substantially vertical layer of silicon nitride. 
     
     
         29 . The semiconductor device of  claim 28 , wherein the substantially vertical layer is removed using a reactive ion etch. 
     
     
         30 . The semiconductor device according to  claim 26 , further comprising a source trench isolation oxide formed between each of the set of fins. 
     
     
         31 . The semiconductor device of  claim 26 , wherein the silicon-based layer comprises silicon oxide (SiO2). 
     
     
         32 . The semiconductor device of  claim 26 , wherein the set of RMG structures comprises polysilicon, silicon-germanium, Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, or CoSi. 
     
     
         33 . The semiconductor device of  claim 26 , wherein the substrate comprises silicon, SiGe, or SOI.