Latch-up robust scr-based devices

Abstract

An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

What is claimed is: 
     
         1 . A device comprising:
 a first n-well region in a substrate for a silicon control rectifier (SCR);   a first N+ region and a first P+ region in the substrate on a first side of the first n-well region;   a second n-well on a second side of the first n-well region that is opposite the first side;   a second N+ region in the first n-well region, and a second P+ region in the second n-well region, wherein the first N+ and P+ regions are coupled to a ground rail, the second N+ region is coupled to a power rail, the second P+ region is coupled to an I/O pad, and a holding voltage of the SCR that is greater than a maximum operating voltage of the SCR during a latch-up event is provided by turning on the power rail;   a third P+ region between the second N+ and P+ regions;   a resistor having first and second resistor terminals;   a capacitor having first and second capacitor terminals; and   the third P+ region is coupled to the first resistor and capacitor terminals, the second resistor terminal is coupled to the ground rail, and the second capacitor terminal is coupled to the I/O pad.   
     
     
         2 . A device comprising:
 a first N+ region and a first P+ region in a substrate;   first and second n-well regions in the substrate proximate the first N+ and P+ regions;   a second N+ region in the first n-well region; and   a second P+ region in the second n-well region, wherein the first N+ and P+ regions are coupled to a ground rail, the second N+ region is coupled to a power rail, and the second P+ region is coupled to an I/O pad.   
     
     
         3 . The device according to  claim 2 , wherein a holding voltage of the device is greater than a maximum operating voltage of the device during a latch-up event. 
     
     
         4 . The device according to  claim 3 , wherein the holding voltage of the device is provided by the power rail being turned on. 
     
     
         5 . The device according to  claim 2 , further comprising:
 a third P+ region in the second n-well region.   
     
     
         6 . The device according to  claim 5 , wherein the third P+ region is between the second N+ and P+ regions. 
     
     
         7 . The device according to  claim 6 , further comprising:
 a third N+ region between the second and third P+ regions.   
     
     
         8 . The device according to  claim 5 , further comprising:
 a resistor having first and second resistor terminals; and   a capacitor having first and second capacitor terminals, wherein the third P+ region is coupled to the first resistor and capacitor terminals, the second resistor terminal is coupled to the ground rail, and the second capacitor terminal is coupled to the I/O pad.   
     
     
         9 . The device according to  claim 2 , wherein the first N+ and P+ regions are on a first side of the first n-well region, and the second n-well region is on a second side of the first n-well region that is opposite the first side. 
     
     
         10 . The device according to  claim 2 , wherein a holding current, a trigger current, or a combination thereof of the SCR is greater than 100 milliamps (mA) during a latch-up event. 
     
     
         11 . A device comprising:
 a first n-well region in a substrate for a silicon control rectifier (SCR);   a first N+ region and a first P+ region in the substrate on a first side of the first n-well region;   a second n-well on a second side of the first n-well region that is opposite the first side;   a second N+ region in the first n-well region, and a second P+ region in the second n-well region, wherein the first N+ and P+ regions are coupled to a ground rail, the second N+ region is coupled to a power rail, the second P+ region is coupled to an I/O pad, and a holding voltage of the SCR that is greater than a maximum operating voltage of the SCR during a latch-up event is provided by turning on the power rail; and   a third P+ region between the second N+ and P+ regions.   
     
     
         12 . The device according to  claim 11 , further comprising a resistor coupled to the third P+ region. 
     
     
         13 . The device according to  claim 12 , wherein the resistor has first and second resistor terminals. 
     
     
         14 . The device according to  claim 13 , wherein the first resistor terminal is coupled to the third P+ region. 
     
     
         15 . The device according to  claim 14 , wherein the second resistor terminal is coupled to the ground rail. 
     
     
         16 . The device according to  claim 11 , further comprising a capacitor coupled to the third P+ region. 
     
     
         17 . The device according to  claim 16 , wherein the capacitor has first and second resistor terminals. 
     
     
         18 . The device according to  claim 17 , wherein the first capacitor terminal is coupled to the third P+ region. 
     
     
         19 . The device according to  claim 18 , wherein the second capacitor terminal is coupled to the I/O pad. 
     
     
         20 . The device according to  claim 11 , further comprising:
 a resistor having first and second resistor terminals;   a capacitor having first and second capacitor terminals; and   the third P+ region is coupled to the first resistor and capacitor terminals, the second resistor terminal is coupled to the ground rail, and the second capacitor terminal is coupled to the I/O pad.