Three dimensional semiconductor device having lateral channel and method of manufacturing the same

Abstract

A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 sequentially stacking a first semiconductor layer and a second semiconductor layer on a substrate;   forming an active line by patterning the second semiconductor layer and the first semiconductor layer;   forming a source region and a drain region in predetermined regions of the active line;   entirely oxidizing the first semiconductor layer constituting the active line, and forming an insulating layer on a surface of the second semiconductor layer;   forming line-shaped dummy patterns crossing the active line to pass through the source region and the drain region;   forming a gate electrode in a region between the line-shaped dummy patterns;   selectively removing the line-shaped dummy pattern passing through the source region; and   forming a line-shaped common source node in a region from which the line-shaped dummy pattern is removed.   
     
     
         2 . The method of  claim 1 , wherein, the first semiconductor layer includes a material having a higher oxidation rate than that of the second semiconductor layer. 
     
     
         3 . The method of  claim 2 , wherein the first semiconductor layer includes a silicon germanium (Site) layer, and the second semiconductor layer includes a silicon (Si) layer. 
     
     
         4 . The method of claim wherein the forming of the gate electrode includes:
 forming a conductive layer to be buried in the region between the line-shaped dummy patterns; and   recessing the conductive layer.   
     
     
         5 . A method of manufacturing a semiconductor device, the method comprising:
 forming an active line layer on a substrate;   forming an active line pattern that extend to a first direction, by patterning the active line layer;   forming a source region and a drain region in predetermined regions of the active line;   forming line-shaped dummy patterns on the active line pattern to pass through the source region and the drain region, wherein the line-shaped dummy patterns extend to a second direction that is substantially perpendicular to the first direction;   forming a gate electrode in a region between the line-shaped dummy patterns, wherein the gate electrode extend in parallel to the second direction;   selectively removing the line-shaped dummy pattern passing through the source region; and   forming a line-shaped common source node in a region from which the line-shaped dummy pattern is removed.   
     
     
         6 . The method of  claim 5 , wherein the forming of he gate electrode includes:
 forming a conductive layer to be buried in the region between the line-shaped dummy patterns; and   recessing the conductive layer.