Recessing and capping of gate structures with varying metal compositions

Abstract

A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.

What is claimed is: 
     
         1 . A device formed by a process comprising:
 forming a dummy gate electrode on a substrate;   forming a hard mask over the dummy gate electrode;   forming spacers on opposite sides of the dummy gate electrode and the hard mask;   forming an interlayer dielectric (ILD) over the substrate adjacent the spacers;   forming a first trench in the ILD down to the dummy gate electrode;   removing the dummy gate electrode to form a second trench below the first trench;   forming a metal gate structure in the first and second trenches;   removing a portion of the metal gate structure from the first trench; and   forming a gate cap over the metal gate structure by filling a remainder of the first trench with dielectric cap material.   
     
     
         2 . The device according to  claim 1 , the process further comprising:
 forming the first trench by removing the hard mask and a portion of the spacers adjacent the hard mask.   
     
     
         3 . The device according to  claim 2 , the process further comprising:
 forming a high-k dielectric layer in the first and second trenches;   forming one or more metal liners, over the high-k dielectric layer, in the first and second trenches; and   forming the metal gate structure over the high-k dielectric layer and the metal liners.   
     
     
         4 . The device according to  claim 3 , the process further comprising:
 recessing the metal liners proximate the ILD, with an etch stop on the spacers, the ILD, the high-k dielectric layer, or a combination thereof subsequent to forming the metal gate structure; and   removing the portion of the metal gate structure during the metal liners recess and removing a second portion of the metal gate structure by etching after the metal liners recess, prior to forming the gate cap.   
     
     
         5 . The device according to  claim 3 , the process further comprising:
 removing the portion of the metal gate structure from the first trench with an etch stop at a top of the second trench; and   removing a portion of the metal liners and the high-k dielectric layer in the first trench adjacent an upper surface of remaining portions of the spacers, prior to forming the gate cap.   
     
     
         6 . The device according to  claim 5 , the process further comprising:
 filling a remainder of the second trench with dielectric cap material in addition to the remainder of the first trench;   removing the ILD after the forming of the gate cap; and   removing the high-k dielectric layer and the metal liners around the gate cap after removing the ILD.   
     
     
         7 . The device according to  claim 2 , the process further comprising:
 forming the first trench to have a first width; and   forming the second trench to have a second width, wherein the first width is greater than the second width.   
     
     
         8 . The device according to  claim 2 , the process further comprising:
 forming the second trench between remaining portions of the spacers after forming the first trench.   
     
     
         9 . The device according to  claim 2 , the process further comprising:
 forming a second hard mask over the hard mask;   forming the spacers on sides of the second hard mask; and   planarizing down to an upper surface of the hard mask prior to forming the first trench.   
     
     
         10 . The device according to  claim 9 , the process further comprising:
 forming the dummy gate electrode of polysilicon, the hard mask of a nitride, and the second hard mask of an oxide.   
     
     
         11 . The device according to  claim 2 , the process further comprising:
 forming the gate cap using a first type of dielectric material and the spacers using a second type of dielectric material.   
     
     
         12 . A device formed by a process comprising:
 forming a dummy electrode on a substrate;   forming a first hard mask of a first material over the dummy electrode;   forming a second hard mask of a second material, different from the first material, over the first hard mask;   forming spacers on opposite sides of the dummy electrode, the first hard mask, and the second hard mask;   forming an interlayer dielectric (ILD) over the substrate adjacent the spacers;   performing chemical mechanical polishing (CMP) on the ILD and the second hard mask down to an upper surface of the first hard mask;   removing the first hard mask and adjacent portions of the spacers to form a first trench in the ILD over the dummy electrode, the first trench having a first width;   removing the dummy electrode to form a second trench below the first trench, the second trench having a second width less than the first width;   forming a metal gate structure in the first and second trenches;   removing a portion of the metal gate structure from the first trench; and   forming a gate cap over the metal gate structure by filling a remainder of the first trench with dielectric cap material.   
     
     
         13 . The device according to  claim 12 , the process further comprising:
 forming a high-k dielectric layer in the first and second trenches;   forming one or more metal liners, over the high-k dielectric layer, in the first and second trenches; and   forming the metal gate structure over the high-k dielectric layer and the metal liners.   
     
     
         14 . The device according to  claim 13 , the process further comprising forming the metal gate structure by:
 filling the first and second trenches with metal gate material over the high-k dielectric layer and the metal liners; and   recess etching the metal liners, metal gate material, or a combination thereof with an etch stop at a top of the first trench.   
     
     
         15 . The device according to  claim 12 , the process further comprising:
 forming the dummy electrode of polysilicon, the first hard mask of a nitride material, and the second hard mask of an oxide material.   
     
     
         16 . A device comprising:
 a substrate;   a metal gate above the substrate;   one or more metal liners around bottom and side surfaces of the metal gate;   a high-k dielectric layer around the one or more metal liners; and   a dielectric gate cap over the substrate and surrounding the metal gate, the one or more metal liners, and the high-k dielectric layer.   
     
     
         17 . The device according to  claim 16 , further comprising:
 an interlayer dielectric (ILD) above the substrate and on a first side of the dielectric gate cap.   
     
     
         18 . The device according to  claim 17 , further comprising:
 a self-aligned contact above the substrate and on a second side of the dielectric gate cap,   wherein the self-aligned contact and ILD are formed over active regions of the substrate.   
     
     
         19 . The device according to  claim 16 , further comprising:
 an oxide above the substrate and on a first side of the dielectric gate cap.   
     
     
         20 . The device according to  claim 19 , further comprising:
 a self-aligned contact above the substrate and on a second side of the dielectric gate cap,   wherein the self-aligned contact and oxide are formed over active regions of the substrate.