Multi-chip Package Module And A Doped Polysilicon Trench For Isolation And Connection

Abstract

A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a silicon layer of substantially single crystal, having a bottom surface and a top surface;   a doped layer forming a terminal near the bottom surface of said layer; and   a trench filled with doped polysilicon with said trench extending from said top surface to said terminal.   
     
     
         2 . The device of  claim 1  wherein said silicon layer comprises a vertical transistor with said terminal being a terminal to said vertical transistor. 
     
     
         3 . The device of  claim 2  wherein said trench is formed by an etch process. 
     
     
         4 . The device of  claim 3  wherein said polysilicon in said trench is doped by diffusion. 
     
     
         5 . The device of  claim 1  wherein said layer is formed of an epitaxial layer of silicon, with said layer formed on a single crystalline substrate. 
     
     
         6 . The device of  claim 5  wherein said terminal is a buried layer between said silicon layer and said substrate. 
     
     
         7 . A semiconductor device comprising:
 a silicon layer of substantially single crystal, having a bottom surface and a top surface;   a plurality of vertical circuit components in said layer between said top surface and said bottom surface; and   a trench filled with doped polysilicon with said trench extending from said top surface to said bottom surface isolating and separating said plurality of circuit components from one another.   
     
     
         8 . The device of  claim 7  wherein said trench is formed by an etch process.  
     
     
         9 . The device of  claim 8  wherein said polysilicon in said trench is doped by diffusion. 
     
     
         10 . The device of  claim 9  wherein said layer is formed of an epitaxial layer of silicon, with said layer formed on a single crystalline substrate. 
     
     
         11 . The device of  claim 10  further comprising a buried layer between said silicon layer and said substrate. 
     
     
         12 . A semiconductor device comprising:
 a silicon layer of substantially single crystal substrate, having a top surface;   an epitaxial layer of silicon on the substrate;   a buried layer between the epitaxial layer and the substrate;   a plurality of circuit components in said epitaxial layer; and   a trench filled with doped polysilicon with said trench extending from the top surface to the buried layer to isolate and separate said plurality of circuit components from one another.   
     
     
         13 . The device of  claim 12  wherein said trench is formed by an etch process. 
     
     
         14 . The device of  claim 13  wherein said polysilicon in said trench is doped by diffusion. 
     
     
         15 . The device of  claim 14  wherein said epitaxial layer is formed on a single crystalline substrate.