US2015340430A1PendingUtilityA1

Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods

Assignee: SOITEC SILICON ON INSULATORPriority: Feb 3, 2011Filed: Aug 4, 2015Published: Nov 26, 2015
Est. expiryFeb 3, 2031(~4.5 yrs left)· nominal 20-yr term from priority
H10P 72/7432H10P 72/7412H10P 14/3421H10P 14/3416H10P 14/3411H10P 14/3408H10P 14/3251H10P 14/3248H10P 72/74H10P 30/204H10P 14/3241H10P 14/2923H10P 14/2921H10P 14/20H10P 30/208H10P 30/206H10D 62/8503H10D 62/8325H10D 62/85H10D 62/83H10H 20/8585H10H 20/0137H10H 20/0133H10H 20/018H01L 29/1608H01L 29/2003H01L 29/26H01L 29/16H01L 29/0603
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Claims

Abstract

Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a composite substrate layer;   a first semiconductor layer disposed over a surface of the composite substrate layer; and   at least one additional semiconductor layer epitaxially deposited over the first semiconductor layer on a side thereof opposite the composite substrate layer;   wherein the composite substrate layer exhibits a CTE closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a metallic contact layer disposed between the composite substrate layer and the first semiconductor layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the composite substrate layer exhibits a CTE within about 5% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the composite substrate layer exhibits a CTE within about 2% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the composite substrate layer exhibits a CTE within about 1% of a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the composite substrate layer has an average thickness of at least about ten microns (10.0 μm). 
     
     
         7 . The semiconductor structure of  claim 6 , wherein the composite substrate layer has an average thickness of between about ten microns (10.0 μm) and about one hundred microns (100.0 μm). 
     
     
         8 . The semiconductor structure of  claim 7 , wherein the first semiconductor layer has an average thickness of about five hundred nanometers (500 nm) or less. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein the first semiconductor layer has an average thickness of about one hundred nanometers (100 nm) or less. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein the at least one additional semiconductor layer has an average total thickness of at least one hundred nanometers (100 nm). 
     
     
         11 . The semiconductor structure of  claim 10 , wherein the at least one additional semiconductor layer has an average total thickness of between about one micron (1.0 μm) and about one hundred microns (100.0 μm). 
     
     
         12 . The semiconductor structure of  claim 11 , wherein the first semiconductor layer comprises a semiconductor material selected from the group consisting of silicon, germanium, III-V semiconductor material, and II-VI semiconductor material. 
     
     
         13 . The semiconductor structure of  claim 11 , wherein the composite substrate layer comprises one of a metal-metal composite material, a ceramic-ceramic composite material, and a metal-ceramic composite material. 
     
     
         14 . The semiconductor structure of  claim 11 , wherein:
 at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises gallium nitride (GaN); and   the composite substrate layer comprises tantalum (Ta) and tungsten (W).   
     
     
         15 . The semiconductor structure of  claim 14 , wherein the at least one additional semiconductor layer comprises gallium nitride (GaN). 
     
     
         16 . The semiconductor structure of  claim 15 , wherein the first semiconductor layer comprises silicon (Si). 
     
     
         17 . The semiconductor structure of  claim 14 , wherein each of the first semiconductor layer and the at least one additional semiconductor layer comprises gallium nitride (GaN). 
     
     
         18 . The semiconductor structure of  claim 1 , wherein:
 at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises silicon (Si); and   the composite substrate layer comprises silicon oxide (SiO 2 ) and aluminum oxide (Al 2 O 3 ).   
     
     
         19 . The semiconductor structure of  claim 18 , wherein the at least one additional semiconductor layer comprises silicon (Si). 
     
     
         20 . The semiconductor structure of  claim 19 , wherein each of the first semiconductor layer and the at least one additional semiconductor layer comprises silicon (Si). 
     
     
         21 . The semiconductor structure of  claim 18 , wherein the composite substrate layer comprises about seventy five percent by volume silicon oxide (SiO 2 ) and about twenty five percent by volume aluminum oxide (Al 2 O 3 ). 
     
     
         22 . The semiconductor structure of  claim 1 , wherein:
 at least one of the first semiconductor layer and the at least one additional semiconductor layer comprises silicon carbide (SiC); and   the composite substrate layer comprises silicon oxide (SO 2 ) and aluminum oxide (Al 2 O 3 ).   
     
     
         23 . The semiconductor structure of  claim 22 , wherein each of the first semiconductor layer and the at least one additional semiconductor layer comprises silicon carbide (SiC). 
     
     
         24 . The semiconductor structure of  claim 22 , wherein the composite substrate layer comprises about forty nine percent by volume silicon oxide (SiO 2 ) and about fifty one percent by volume aluminum oxide (Al 2 O 3 ).

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