Integrated circuit including a semiconductor-on-insulator region and a bulk region

Abstract

A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

1 . A structure, comprising:
 a semiconductor substrate;   a semiconductor-on-insulator region, said semiconductor-on-insulator region comprising a first semiconductor region that contains a first active region, a dielectric layer provided between said semiconductor substrate and said first semiconductor region, and a first transistor positioned in and above said first active region in said first semiconductor region, said dielectric layer providing electrical isolation between said first semiconductor region and said semiconductor substrate; and   a bulk region, said bulk region comprising a second semiconductor region provided directly on said semiconductor substrate.   
     
     
         2 . The structure of  claim 1 , wherein said bulk region comprises a second transistor positioned in and above a second active region defined in said second semiconductor region. 
     
     
         3 . The structure of  claim 2 , wherein said second transistor is adapted for operation at a greater supply voltage than said first transistor. 
     
     
         4 . The structure of  claim 1 , wherein said bulk region comprises at least one of a diode and a capacitor. 
     
     
         5 . The structure of  claim 1 , wherein said first transistor is a fully depleted field effect transistor. 
     
     
         6 . The structure of  claim 1 , wherein said semiconductor substrate is a semiconductor die. 
     
     
         7 . The structure of  claim 1 , further comprising a trench isolation structure providing electrical isolation between said first semiconductor region and said second semiconductor region. 
     
     
         8 . The structure of  claim 1 , wherein at least a portion of said second semiconductor region comprises at least one semiconductor material that is different from a material of said semiconductor substrate. 
     
     
         9 . The structure of  claim 8 , wherein said semiconductor substrate comprises silicon and said portion of said second semiconductor region comprises at least one of silicon/germanium, germanium and one or more III-V semiconductor materials. 
     
     
         10 . The structure of  claim 8 , wherein said second semiconductor region comprises a high electron mobility transistor. 
     
     
         11 . The structure of  claim 8 , further comprising a digital logic circuit, at least a part of said digital logic circuit being provided in said semiconductor-on-insulator region, and a high frequency analog circuit, at least a part of said high frequency analog circuit being provided in said bulk region. 
     
     
         12 .- 23 . (canceled) 
     
     
         24 . A structure, comprising:
 a silicon substrate;   a semiconductor-on-insulator region, said semiconductor-on-insulator region comprising a layer of silicon that contains a first active region, a dielectric layer between and in contact with an upper surface of said silicon substrate and a lower surface of said layer of silicon, wherein said dielectric layer provides electrical isolation between said first active region and said silicon substrate;   a first transistor positioned in and above said first active region in said layer of silicon;   a bulk region comprised of at least one semiconductor material, said bulk region comprising a second active region, wherein a portion of said at least one semiconductor material is positioned on and in contact with said silicon substrate;   a trench isolation structure providing electrical isolation between said first active region and said second active region; and   a semiconductor device positioned at least partially in said second active region.   
     
     
         25 . The structure of  claim 24 , wherein said semiconductor device is a second transistor. 
     
     
         26 . The structure of  claim 25 , wherein said second transistor is adapted for operation at a greater supply voltage than said first transistor. 
     
     
         27 . The structure of  claim 24 , wherein said semiconductor device is one of a diode or a capacitor. 
     
     
         28 . The structure of  claim 24 , wherein said first transistor is a fully depleted field effect transistor. 
     
     
         29 . The structure of  claim 24 , wherein said at least one semiconductor material in said bulk region comprises a layer of silicon positioned on and in contact with said silicon substrate and at least one additional semiconductor material positioned above said layer of silicon. 
     
     
         30 . The structure of  claim 24 , wherein said at least one semiconductor material in said bulk region comprises at least one semiconductor material that is different from said silicon substrate. 
     
     
         31 . The structure of  claim 24 , wherein said at least one semiconductor material in said bulk region comprises at least one of silicon/germanium, germanium and one or more III-V semiconductor materials. 
     
     
         32 . The structure of  claim 24 , wherein said semiconductor device is a high electron mobility transistor.