Semiconductor device

Abstract

A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a wiring board including an upper surface, a plurality of upper electrodes formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of lower electrodes formed on the lower surface and also respectively electrically connected with the plurality of upper electrodes;   a first chip including a first front surface, a plurality of first front electrodes formed on the first front surface, a first back surface opposite to the first front surface, a plurality of first penetrating electrodes extending from the first back surface toward the first front surface, and a plurality of first back electrodes formed on the first back surface and also respectively electrically connected with the plurality of first front electrodes via the plurality of first penetrating electrodes, and mounted on the first surface of the wiring board such that the first front surface of the first chip faces the first surface of the wiring board;   a second chip including a second front surface, a plurality of second front electrodes formed on the second front surface, a second back surface opposite to the second front surface, a plurality of second penetrating electrodes extending from the second back surface toward the second front surface, and a plurality of second back electrodes formed on the second back surface and also respectively electrically connected with the plurality of second front electrodes via the plurality of second penetrating electrodes, and mounted on the first back surface of the first chip such that the second front surface of the second chip faces the first back surface of the first chip; and   a third chip including a third front surface, and a plurality of third front electrodes formed on the third front surface, and mounted on the second back surface of the second chip such that the third front surface of the third chip faces the second back surface of the second chip,   wherein each of the first and third chips has a circuit,   wherein the plurality of third front electrodes are electrically connected with the plurality of lower electrodes via the plurality of second back electrodes, the plurality of second penetrating electrodes, the plurality of second front electrodes, the plurality of first back electrodes, the plurality of first penetrating electrodes, the plurality of first front electrodes, and the plurality of upper electrodes, respectively,   wherein a planar area of the second chip is larger than a planar are of the first chip in a plan view, and   wherein a planar area of the third chip is larger than the planar area of the second chip in the plan view.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein the second chip has no circuits. 
     
     
         23 . The semiconductor device according to  claim 21 ,
 wherein the plurality of first front electrodes includes a first inner electrode, and a first outer electrode located closer than the first inner electrode to a peripheral portion of the first front surface,   wherein the plurality of first back electrodes includes a second inner electrode, and a second outer electrode located closer than the second inner electrode to a peripheral portion of the first back surface,   wherein the plurality of second front electrodes includes a third inner electrode, and a third outer electrode located closer than the third inner electrode to a peripheral portion of the second front surface,   wherein the plurality of second back electrodes includes a fourth inner electrode and a fourth outer electrode located closer than the fourth inner electrode to a peripheral portion of the second back surface,   wherein the second inner electrode is overlapped with the first inner electrode,   wherein the second outer electrode is overlapped with the first outer electrode,   wherein the fourth inner electrode is overlapped with the third inner electrode, and   wherein the fourth outer electrode is overlapped with the third outer electrode.   
     
     
         24 . The semiconductor device according to  claim 23 ,
 wherein the fourth outer electrode is electrically connected with the third outer electrode via an outer penetrating electrode of the plurality of second penetrating electrodes and a wiring line formed on one of the second front surface and the second back surface.   
     
     
         25 . The semiconductor device according to  claim 21 ,
 wherein the plurality of second front electrodes are electrically connected with the plurality of first back electrodes via a plurality of first solder materials, respectively, and   wherein the plurality of third front electrodes are electrically connected with the plurality of second back electrodes via a plurality of second solder materials, respectively.   
     
     
         26 . The semiconductor device according to  claim 21 ,
 wherein the plurality of first solder materials are sealed with a first resin material, and   wherein the plurality of second solder materials are sealed with a second resin material.